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shader_recompiler: Implement FREXP instructions. (#1766)

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squidbus 2024-12-13 11:51:39 -08:00 • committed by GitHub
parent 722a0e36be
commit f1c23d514b
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10 changed files with 119 additions and 8 deletions
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2
externals/sirit vendored

@ -1 +1 @@
Subproject commit 6cecb95d679c82c413d1f989e0b7ad9af130600d
Subproject commit e12b6b592ce9917a85303c555259488643c56f47

26
src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp
View file

@ -225,10 +225,34 @@ Id EmitFPTrunc64(EmitContext& ctx, Id value) {
return ctx.OpTrunc(ctx.F64[1], value);
}
Id EmitFPFract(EmitContext& ctx, Id value) {
Id EmitFPFract32(EmitContext& ctx, Id value) {
return ctx.OpFract(ctx.F32[1], value);
}
Id EmitFPFract64(EmitContext& ctx, Id value) {
return ctx.OpFract(ctx.F64[1], value);
}
Id EmitFPFrexpSig32(EmitContext& ctx, Id value) {
const auto frexp = ctx.OpFrexpStruct(ctx.frexp_result_f32, value);
return ctx.OpCompositeExtract(ctx.F32[1], frexp, 0);
}
Id EmitFPFrexpSig64(EmitContext& ctx, Id value) {
const auto frexp = ctx.OpFrexpStruct(ctx.frexp_result_f64, value);
return ctx.OpCompositeExtract(ctx.F64[1], frexp, 0);
}
Id EmitFPFrexpExp32(EmitContext& ctx, Id value) {
const auto frexp = ctx.OpFrexpStruct(ctx.frexp_result_f32, value);
return ctx.OpCompositeExtract(ctx.U32[1], frexp, 1);
}
Id EmitFPFrexpExp64(EmitContext& ctx, Id value) {
const auto frexp = ctx.OpFrexpStruct(ctx.frexp_result_f64, value);
return ctx.OpCompositeExtract(ctx.U32[1], frexp, 1);
}
Id EmitFPOrdEqual16(EmitContext& ctx, Id lhs, Id rhs) {
return ctx.OpFOrdEqual(ctx.U1[1], lhs, rhs);
}

7
src/shader_recompiler/backend/spirv/emit_spirv_instructions.h
View file

@ -222,7 +222,12 @@ Id EmitFPCeil64(EmitContext& ctx, Id value);
Id EmitFPTrunc16(EmitContext& ctx, Id value);
Id EmitFPTrunc32(EmitContext& ctx, Id value);
Id EmitFPTrunc64(EmitContext& ctx, Id value);
Id EmitFPFract(EmitContext& ctx, Id value);
Id EmitFPFract32(EmitContext& ctx, Id value);
Id EmitFPFract64(EmitContext& ctx, Id value);
Id EmitFPFrexpSig32(EmitContext& ctx, Id value);
Id EmitFPFrexpSig64(EmitContext& ctx, Id value);
Id EmitFPFrexpExp32(EmitContext& ctx, Id value);
Id EmitFPFrexpExp64(EmitContext& ctx, Id value);
Id EmitFPOrdEqual16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdEqual32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdEqual64(EmitContext& ctx, Id lhs, Id rhs);

4
src/shader_recompiler/backend/spirv/spirv_emit_context.cpp
View file

@ -147,6 +147,10 @@ void EmitContext::DefineArithmeticTypes() {
full_result_i32x2 = Name(TypeStruct(S32[1], S32[1]), "full_result_i32x2");
full_result_u32x2 = Name(TypeStruct(U32[1], U32[1]), "full_result_u32x2");
frexp_result_f32 = Name(TypeStruct(F32[1], U32[1]), "frexp_result_f32");
if (info.uses_fp64) {
frexp_result_f64 = Name(TypeStruct(F64[1], U32[1]), "frexp_result_f64");
}
}
void EmitContext::DefineInterfaces() {

2
src/shader_recompiler/backend/spirv/spirv_emit_context.h
View file

@ -148,6 +148,8 @@ public:
Id full_result_i32x2;
Id full_result_u32x2;
Id frexp_result_f32;
Id frexp_result_f64;
Id pi_x2;

5
src/shader_recompiler/frontend/translate/translate.h
View file

@ -200,6 +200,11 @@ public:
void V_BFREV_B32(const GcnInst& inst);
void V_FFBH_U32(const GcnInst& inst);
void V_FFBL_B32(const GcnInst& inst);
void V_FREXP_EXP_I32_F64(const GcnInst& inst);
void V_FREXP_MANT_F64(const GcnInst& inst);
void V_FRACT_F64(const GcnInst& inst);
void V_FREXP_EXP_I32_F32(const GcnInst& inst);
void V_FREXP_MANT_F32(const GcnInst& inst);
void V_MOVRELD_B32(const GcnInst& inst);
void V_MOVRELS_B32(const GcnInst& inst);
void V_MOVRELSD_B32(const GcnInst& inst);

37
src/shader_recompiler/frontend/translate/vector_alu.cpp
View file

@ -179,6 +179,16 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
return V_FFBH_U32(inst);
case Opcode::V_FFBL_B32:
return V_FFBL_B32(inst);
case Opcode::V_FREXP_EXP_I32_F64:
return V_FREXP_EXP_I32_F64(inst);
case Opcode::V_FREXP_MANT_F64:
return V_FREXP_MANT_F64(inst);
case Opcode::V_FRACT_F64:
return V_FRACT_F64(inst);
case Opcode::V_FREXP_EXP_I32_F32:
return V_FREXP_EXP_I32_F32(inst);
case Opcode::V_FREXP_MANT_F32:
return V_FREXP_MANT_F32(inst);
case Opcode::V_MOVRELD_B32:
return V_MOVRELD_B32(inst);
case Opcode::V_MOVRELS_B32:
@ -733,7 +743,7 @@ void Translator::V_CVT_F32_UBYTE(u32 index, const GcnInst& inst) {
void Translator::V_FRACT_F32(const GcnInst& inst) {
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
SetDst(inst.dst[0], ir.Fract(src0));
SetDst(inst.dst[0], ir.FPFract(src0));
}
void Translator::V_TRUNC_F32(const GcnInst& inst) {
@ -822,6 +832,31 @@ void Translator::V_FFBL_B32(const GcnInst& inst) {
SetDst(inst.dst[0], ir.FindILsb(src0));
}
void Translator::V_FREXP_EXP_I32_F64(const GcnInst& inst) {
const IR::F64 src0{GetSrc64<IR::F64>(inst.src[0])};
SetDst(inst.dst[0], ir.FPFrexpExp(src0));
}
void Translator::V_FREXP_MANT_F64(const GcnInst& inst) {
const IR::F64 src0{GetSrc64<IR::F64>(inst.src[0])};
SetDst64(inst.dst[0], ir.FPFrexpSig(src0));
}
void Translator::V_FRACT_F64(const GcnInst& inst) {
const IR::F32 src0{GetSrc64<IR::F64>(inst.src[0])};
SetDst64(inst.dst[0], ir.FPFract(src0));
}
void Translator::V_FREXP_EXP_I32_F32(const GcnInst& inst) {
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
SetDst(inst.dst[0], ir.FPFrexpExp(src0));
}
void Translator::V_FREXP_MANT_F32(const GcnInst& inst) {
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
SetDst(inst.dst[0], ir.FPFrexpSig(src0));
}
void Translator::V_MOVRELD_B32(const GcnInst& inst) {
const IR::U32 src_val{GetSrc(inst.src[0])};
u32 dst_vgprno = inst.dst[0].code - static_cast<u32>(IR::VectorReg::V0);

33
src/shader_recompiler/ir/ir_emitter.cpp
View file

@ -869,8 +869,37 @@ F32F64 IREmitter::FPTrunc(const F32F64& value) {
}
}
F32 IREmitter::Fract(const F32& value) {
return Inst<F32>(Opcode::FPFract, value);
F32F64 IREmitter::FPFract(const F32F64& value) {
switch (value.Type()) {
case Type::F32:
return Inst<F32>(Opcode::FPFract32, value);
case Type::F64:
return Inst<F64>(Opcode::FPFract64, value);
default:
ThrowInvalidType(value.Type());
}
}
F32F64 IREmitter::FPFrexpSig(const F32F64& value) {
switch (value.Type()) {
case Type::F32:
return Inst<F32>(Opcode::FPFrexpSig32, value);
case Type::F64:
return Inst<F64>(Opcode::FPFrexpSig64, value);
default:
ThrowInvalidType(value.Type());
}
}
U32 IREmitter::FPFrexpExp(const F32F64& value) {
switch (value.Type()) {
case Type::F32:
return Inst<U32>(Opcode::FPFrexpExp32, value);
case Type::F64:
return Inst<U32>(Opcode::FPFrexpExp64, value);
default:
ThrowInvalidType(value.Type());
}
}
U1 IREmitter::FPEqual(const F32F64& lhs, const F32F64& rhs, bool ordered) {

4
src/shader_recompiler/ir/ir_emitter.h
View file

@ -180,7 +180,9 @@ public:
[[nodiscard]] F32F64 FPFloor(const F32F64& value);
[[nodiscard]] F32F64 FPCeil(const F32F64& value);
[[nodiscard]] F32F64 FPTrunc(const F32F64& value);
[[nodiscard]] F32 Fract(const F32& value);
[[nodiscard]] F32F64 FPFract(const F32F64& value);
[[nodiscard]] F32F64 FPFrexpSig(const F32F64& value);
[[nodiscard]] U32 FPFrexpExp(const F32F64& value);
[[nodiscard]] U1 FPEqual(const F32F64& lhs, const F32F64& rhs, bool ordered = true);
[[nodiscard]] U1 FPNotEqual(const F32F64& lhs, const F32F64& rhs, bool ordered = true);

7
src/shader_recompiler/ir/opcodes.inc
View file

@ -210,7 +210,12 @@ OPCODE(FPCeil32, F32, F32,
OPCODE(FPCeil64, F64, F64, )
OPCODE(FPTrunc32, F32, F32, )
OPCODE(FPTrunc64, F64, F64, )
OPCODE(FPFract, F32, F32, )
OPCODE(FPFract32, F32, F32, )
OPCODE(FPFract64, F64, F64, )
OPCODE(FPFrexpSig32, F32, F32, )
OPCODE(FPFrexpSig64, F64, F64, )
OPCODE(FPFrexpExp32, U32, F32, )
OPCODE(FPFrexpExp64, U32, F64, )
OPCODE(FPOrdEqual32, U1, F32, F32, )
OPCODE(FPOrdEqual64, U1, F64, F64, )