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Fixed minicoro.h formatting

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This commit is contained in:
darktux 2024-04-05 01:58:30 +02:00
parent 7e44e3d471
commit 40824a903d
1 changed files with 103 additions and 103 deletions
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206
src/common/minicoro.h
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@ -823,10 +823,10 @@ __asm__(".text\n"
".globl __mco_wrap_main\n"
"__mco_wrap_main:\n"
#else /* Linux assembler */
".globl _mco_wrap_main\n"
".type _mco_wrap_main @function\n"
".hidden _mco_wrap_main\n"
"_mco_wrap_main:\n"
".globl _mco_wrap_main\n"
".type _mco_wrap_main @function\n"
".hidden _mco_wrap_main\n"
"_mco_wrap_main:\n"
#endif
" movq %r13, %rdi\n"
" jmpq *%r12\n"
@ -840,10 +840,10 @@ __asm__(".text\n"
".globl __mco_switch\n"
"__mco_switch:\n"
#else /* Linux assembler */
".globl _mco_switch\n"
".type _mco_switch @function\n"
".hidden _mco_switch\n"
"_mco_switch:\n"
".globl _mco_switch\n"
".type _mco_switch @function\n"
".hidden _mco_switch\n"
"_mco_switch:\n"
#endif
" leaq 0x3d(%rip), %rax\n"
" movq %rax, (%rdi)\n"
@ -979,92 +979,92 @@ __asm__(".text\n"
" ld sp, 0x70(a1)\n"
" jr a2\n"
#elif __riscv_xlen == 32
" sw s0, 0x00(a0)\n"
" sw s1, 0x04(a0)\n"
" sw s2, 0x08(a0)\n"
" sw s3, 0x0c(a0)\n"
" sw s4, 0x10(a0)\n"
" sw s5, 0x14(a0)\n"
" sw s6, 0x18(a0)\n"
" sw s7, 0x1c(a0)\n"
" sw s8, 0x20(a0)\n"
" sw s9, 0x24(a0)\n"
" sw s10, 0x28(a0)\n"
" sw s11, 0x2c(a0)\n"
" sw ra, 0x30(a0)\n"
" sw ra, 0x34(a0)\n" /* pc */
" sw sp, 0x38(a0)\n"
" sw s0, 0x00(a0)\n"
" sw s1, 0x04(a0)\n"
" sw s2, 0x08(a0)\n"
" sw s3, 0x0c(a0)\n"
" sw s4, 0x10(a0)\n"
" sw s5, 0x14(a0)\n"
" sw s6, 0x18(a0)\n"
" sw s7, 0x1c(a0)\n"
" sw s8, 0x20(a0)\n"
" sw s9, 0x24(a0)\n"
" sw s10, 0x28(a0)\n"
" sw s11, 0x2c(a0)\n"
" sw ra, 0x30(a0)\n"
" sw ra, 0x34(a0)\n" /* pc */
" sw sp, 0x38(a0)\n"
#ifdef __riscv_flen
#if __riscv_flen == 64
" fsd fs0, 0x3c(a0)\n"
" fsd fs1, 0x44(a0)\n"
" fsd fs2, 0x4c(a0)\n"
" fsd fs3, 0x54(a0)\n"
" fsd fs4, 0x5c(a0)\n"
" fsd fs5, 0x64(a0)\n"
" fsd fs6, 0x6c(a0)\n"
" fsd fs7, 0x74(a0)\n"
" fsd fs8, 0x7c(a0)\n"
" fsd fs9, 0x84(a0)\n"
" fsd fs10, 0x8c(a0)\n"
" fsd fs11, 0x94(a0)\n"
" fld fs0, 0x3c(a1)\n"
" fld fs1, 0x44(a1)\n"
" fld fs2, 0x4c(a1)\n"
" fld fs3, 0x54(a1)\n"
" fld fs4, 0x5c(a1)\n"
" fld fs5, 0x64(a1)\n"
" fld fs6, 0x6c(a1)\n"
" fld fs7, 0x74(a1)\n"
" fld fs8, 0x7c(a1)\n"
" fld fs9, 0x84(a1)\n"
" fld fs10, 0x8c(a1)\n"
" fld fs11, 0x94(a1)\n"
" fsd fs0, 0x3c(a0)\n"
" fsd fs1, 0x44(a0)\n"
" fsd fs2, 0x4c(a0)\n"
" fsd fs3, 0x54(a0)\n"
" fsd fs4, 0x5c(a0)\n"
" fsd fs5, 0x64(a0)\n"
" fsd fs6, 0x6c(a0)\n"
" fsd fs7, 0x74(a0)\n"
" fsd fs8, 0x7c(a0)\n"
" fsd fs9, 0x84(a0)\n"
" fsd fs10, 0x8c(a0)\n"
" fsd fs11, 0x94(a0)\n"
" fld fs0, 0x3c(a1)\n"
" fld fs1, 0x44(a1)\n"
" fld fs2, 0x4c(a1)\n"
" fld fs3, 0x54(a1)\n"
" fld fs4, 0x5c(a1)\n"
" fld fs5, 0x64(a1)\n"
" fld fs6, 0x6c(a1)\n"
" fld fs7, 0x74(a1)\n"
" fld fs8, 0x7c(a1)\n"
" fld fs9, 0x84(a1)\n"
" fld fs10, 0x8c(a1)\n"
" fld fs11, 0x94(a1)\n"
#elif __riscv_flen == 32
" fsw fs0, 0x3c(a0)\n"
" fsw fs1, 0x40(a0)\n"
" fsw fs2, 0x44(a0)\n"
" fsw fs3, 0x48(a0)\n"
" fsw fs4, 0x4c(a0)\n"
" fsw fs5, 0x50(a0)\n"
" fsw fs6, 0x54(a0)\n"
" fsw fs7, 0x58(a0)\n"
" fsw fs8, 0x5c(a0)\n"
" fsw fs9, 0x60(a0)\n"
" fsw fs10, 0x64(a0)\n"
" fsw fs11, 0x68(a0)\n"
" flw fs0, 0x3c(a1)\n"
" flw fs1, 0x40(a1)\n"
" flw fs2, 0x44(a1)\n"
" flw fs3, 0x48(a1)\n"
" flw fs4, 0x4c(a1)\n"
" flw fs5, 0x50(a1)\n"
" flw fs6, 0x54(a1)\n"
" flw fs7, 0x58(a1)\n"
" flw fs8, 0x5c(a1)\n"
" flw fs9, 0x60(a1)\n"
" flw fs10, 0x64(a1)\n"
" flw fs11, 0x68(a1)\n"
" fsw fs0, 0x3c(a0)\n"
" fsw fs1, 0x40(a0)\n"
" fsw fs2, 0x44(a0)\n"
" fsw fs3, 0x48(a0)\n"
" fsw fs4, 0x4c(a0)\n"
" fsw fs5, 0x50(a0)\n"
" fsw fs6, 0x54(a0)\n"
" fsw fs7, 0x58(a0)\n"
" fsw fs8, 0x5c(a0)\n"
" fsw fs9, 0x60(a0)\n"
" fsw fs10, 0x64(a0)\n"
" fsw fs11, 0x68(a0)\n"
" flw fs0, 0x3c(a1)\n"
" flw fs1, 0x40(a1)\n"
" flw fs2, 0x44(a1)\n"
" flw fs3, 0x48(a1)\n"
" flw fs4, 0x4c(a1)\n"
" flw fs5, 0x50(a1)\n"
" flw fs6, 0x54(a1)\n"
" flw fs7, 0x58(a1)\n"
" flw fs8, 0x5c(a1)\n"
" flw fs9, 0x60(a1)\n"
" flw fs10, 0x64(a1)\n"
" flw fs11, 0x68(a1)\n"
#else
#error "Unsupported RISC-V FLEN"
#endif
#endif /* __riscv_flen */
" lw s0, 0x00(a1)\n"
" lw s1, 0x04(a1)\n"
" lw s2, 0x08(a1)\n"
" lw s3, 0x0c(a1)\n"
" lw s4, 0x10(a1)\n"
" lw s5, 0x14(a1)\n"
" lw s6, 0x18(a1)\n"
" lw s7, 0x1c(a1)\n"
" lw s8, 0x20(a1)\n"
" lw s9, 0x24(a1)\n"
" lw s10, 0x28(a1)\n"
" lw s11, 0x2c(a1)\n"
" lw ra, 0x30(a1)\n"
" lw a2, 0x34(a1)\n" /* pc */
" lw sp, 0x38(a1)\n"
" jr a2\n"
" lw s0, 0x00(a1)\n"
" lw s1, 0x04(a1)\n"
" lw s2, 0x08(a1)\n"
" lw s3, 0x0c(a1)\n"
" lw s4, 0x10(a1)\n"
" lw s5, 0x14(a1)\n"
" lw s6, 0x18(a1)\n"
" lw s7, 0x1c(a1)\n"
" lw s8, 0x20(a1)\n"
" lw s9, 0x24(a1)\n"
" lw s10, 0x28(a1)\n"
" lw s11, 0x2c(a1)\n"
" lw ra, 0x30(a1)\n"
" lw a2, 0x34(a1)\n" /* pc */
" lw sp, 0x38(a1)\n"
" jr a2\n"
#else
#error "Unsupported RISC-V XLEN"
#endif /* __riscv_xlen */
@ -1157,10 +1157,10 @@ __asm__(".text\n"
".globl __mco_switch\n"
"__mco_switch:\n"
#else
".globl _mco_switch\n"
".type _mco_switch #function\n"
".hidden _mco_switch\n"
"_mco_switch:\n"
".globl _mco_switch\n"
".type _mco_switch #function\n"
".hidden _mco_switch\n"
"_mco_switch:\n"
#endif
#ifndef __SOFTFP__
" vstmia r0!, {d8-d15}\n"
@ -1182,10 +1182,10 @@ __asm__(".text\n"
".globl __mco_wrap_main\n"
"__mco_wrap_main:\n"
#else
".globl _mco_wrap_main\n"
".type _mco_wrap_main #function\n"
".hidden _mco_wrap_main\n"
"_mco_wrap_main:\n"
".globl _mco_wrap_main\n"
".type _mco_wrap_main #function\n"
".hidden _mco_wrap_main\n"
"_mco_wrap_main:\n"
#endif
" mov r0, r4\n"
" mov ip, r5\n"
@ -1223,10 +1223,10 @@ __asm__(".text\n"
".globl __mco_switch\n"
"__mco_switch:\n"
#else
".globl _mco_switch\n"
".type _mco_switch #function\n"
".hidden _mco_switch\n"
"_mco_switch:\n"
".globl _mco_switch\n"
".type _mco_switch #function\n"
".hidden _mco_switch\n"
"_mco_switch:\n"
#endif
" mov x10, sp\n"
@ -1265,10 +1265,10 @@ __asm__(".text\n"
".globl __mco_wrap_main\n"
"__mco_wrap_main:\n"
#else
".globl _mco_wrap_main\n"
".type _mco_wrap_main #function\n"
".hidden _mco_wrap_main\n"
"_mco_wrap_main:\n"
".globl _mco_wrap_main\n"
".type _mco_wrap_main #function\n"
".hidden _mco_wrap_main\n"
"_mco_wrap_main:\n"
#endif
" mov x0, x19\n"
" mov x30, x21\n"