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mc.h switch from enum to struct

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Resaec 2018-04-26 00:30:16 +02:00
parent 5565a2d131
commit 79b4b608e5
1 changed files with 56 additions and 60 deletions
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116
exosphere/src/mc.h
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@ -48,79 +48,75 @@ typedef struct {
} security_carveout_t;
/* 18.11.1 MC Registers */
typedef enum {
MC_REGISTER_SMMU_CONFIG_0 = 0x10,
MC_REGISTER_SMMU_TLB_CONFIG_0 = 0x14, /* Controls usage of the TLB */
MC_REGISTER_SMMU_PTC_CONFIG_0 = 0x18, /* Controls usage of the PTC */
MC_REGISTER_SMMU_PTB_ASID_0 = 0x1C,
MC_REGISTER_SMMU_PTB_DATA_0 = 0x20,
MC_REGISTER_SMMU_TLB_FLUSH_0 = 0x30,
MC_REGISTER_SMMU_PTC_FLUSH_0 = 0x34,
MC_REGISTER_0x38 = 0x38,
MC_REGISTER_0x3C = 0x3C,
typedef struct {
uint32_t _0x0[4];
uint32_t SMMU_CONFIG_0;
uint32_t SMMU_TLB_CONFIG_0; /* Controls usage of the TLB */
uint32_t SMMU_PTC_CONFIG_0; /* Controls usage of the PTC */
uint32_t SMMU_PTB_ASID_0;
uint32_t SMMU_PTB_DATA_0;
uint32_t _0x24[3];
uint32_t SMMU_TLB_FLUSH_0;
uint32_t SMMU_PTC_FLUSH_0;
uint32_t _0x38;
uint32_t _0x3C;
uint32_t _0x40[12];
/* SECURITY_BOM is the base of the secured region, limited to MB granularity.
This must point to a region of the physical address map allocated to EMEM for it to be effective; the MC cannot secure address space it does not own. (In other words, this is an absolute address, not an offset.)
Above is the list of clients with the TrustZone-security access. [18.11.1.20]
Note that AXICIF clients will adhere to the standard AXI protocol "aprot[1]==0" indication for secure requests. */
MC_REGISTER_SECURITY_BOM = 0x70,
MC_REGISTER_SECURITY_CFG0_0 = MC_REGISTER_SECURITY_BOM,
MC_REGISTER_SECURITY_SIZE_MB = 0x74, /* SECURITY_SIZE_MB is the size, in megabytes, of the secured region. If set to 0, the security check in MC is disabled */
MC_REGISTER_SECURITY_CFG1_0 = MC_REGISTER_SECURITY_SIZE_MB,
MC_REGISTER_EMEM_ARB_RING1_THROTTLE_0 = 0xE0,
MC_REGISTER_EMEM_ARB_RING3_THROTTLE_0 = 0xE4,
MC_REGISTER_EMEM_ARB_OVERRIDE_0 = 0xE8,
MC_REGISTER_EMEM_ARB_RSV_0 = 0xEC,
MC_REGISTER_0xF0 = 0xF0,
MC_REGISTER_CLKEN_OVERRIDE_0 = 0xF4,
MC_REGISTER_SMMU_TRANSLATION_ENABLE_0_0 = 0x228,
MC_REGISTER_SMMU_TRANSLATION_ENABLE_1_0 = 0x22C,
MC_REGISTER_SMMU_TRANSLATION_ENABLE_2_0 = 0x230,
MC_REGISTER_SMMU_TRANSLATION_ENABLE_3_0 = 0x234,
MC_REGISTER_SMMU_AVPC_ASID_0 = 0x23C,
MC_REGISTER_SMMU_PPCS1_ASID_0 = 0x298,
MC_REGISTER_0x648 = 0x648,
MC_REGISTER_0x64C = 0x64C,
MC_REGISTER_0x650 = 0x650,
MC_REGISTER_0x65C = 0x65C,
MC_REGISTER_0x660 = 0x660,
MC_REGISTER_IRAM_REG_CTRL_0 = 0x964,
MC_REGISTER_EMEM_CFG_ACCESS_CTRL_0 = MC_REGISTER_IRAM_REG_CTRL_0,
MC_REGISTER_SEC_CARVEOUT_BOM_0 = 0x670, /* [PMC_SECURE] Base address for the SEC carveout address space */
MC_REGISTER_SEC_CARVEOUT_SIZE_MB_0 = 0x674, /* [PMC_SECURE] SEC_CARVEOUT_SIZE_MB is the size, in megabytes, of the SEC carveout region. If set to 0, the security check in MC is disabled */
uint32_t SECURITY_BOM;
uint32_t SECURITY_SIZE_MB; /* SECURITY_SIZE_MB is the size, in megabytes, of the secured region. If set to 0, the security check in MC is disabled */
uint32_t _0x78[26];
uint32_t EMEM_ARB_RING1_THROTTLE_0;
uint32_t EMEM_ARB_RING3_THROTTLE_0;
uint32_t EMEM_ARB_OVERRIDE_0;
uint32_t EMEM_ARB_RSV_0;
uint32_t _0xF0;
uint32_t CLKEN_OVERRIDE_0;
uint32_t _0xF8[76];
uint32_t SMMU_TRANSLATION_ENABLE_0_0;
uint32_t SMMU_TRANSLATION_ENABLE_1_0;
uint32_t SMMU_TRANSLATION_ENABLE_2_0;
uint32_t SMMU_TRANSLATION_ENABLE_3_0;
uint32_t _0x234[1];
uint32_t SMMU_AVPC_ASID_0;
uint32_t _0x240[22];
uint32_t SMMU_PPCS1_ASID_0;
uint32_t _0x29C[235];
uint32_t _0x648;
uint32_t _0x64C;
uint32_t _0x650;
uint32_t _0x654[2];
uint32_t _0x65C;
uint32_t _0x660;
uint32_t _0x664[3];
uint32_t SEC_CARVEOUT_BOM_0; /* [PMC_SECURE] Base address for the SEC carveout address space */
uint32_t SEC_CARVEOUT_SIZE_MB_0; /* [PMC_SECURE] SEC_CARVEOUT_SIZE_MB is the size, in megabytes, of the SEC carveout region. If set to 0, the security check in MC is disabled */
/* [PMC_SECURE] Sticky bit to control the writes to the other Sec Carveout aperture registers
0 = Enabled
1 = Disabled */
MC_REGISTER_SEC_CARVEOUT_REG_CTRL_0 = 0x678,
MC_REGISTER_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x984,
MC_REGISTER_MTS_CARVEOUT_BOM_0 = 0x9A0,
MC_REGISTER_MTS_CARVEOUT_SIZE_MB_0 = 0x9A4,
MC_REGISTER_MTS_CARVEOUT_ADR_HI_0 = 0x9A8,
uint32_t SEC_CARVEOUT_REG_CTRL_0;
uint32_t _0x67C[186];
uint32_t EMEM_CFG_ACCESS_CTRL_0_AND_IRAM_REG_CTRL_0;
uint32_t _0x968[7];
uint32_t VIDEO_PROTECT_GPU_OVERRIDE_0_0;
uint32_t _0x988[6];
uint32_t MTS_CARVEOUT_BOM_0;
uint32_t MTS_CARVEOUT_SIZE_MB_0;
uint32_t MTS_CARVEOUT_ADR_HI_0;
/* MTS_CARVEOUT_WRITE_ACCESS
0 = Enabled
1 = Disabled */
MC_REGISTER_MTS_CARVEOUT_REG_CTRL_0 = 0x9AC,
uint32_t MTS_CARVEOUT_REG_CTRL_0;
uint32_t _0x9B0[3];
/* Base Address Higher Bits
SECURITY_BOM_HI has the higher address bits beyond 32 bits of the
base of the secured region, limited to MB granularity */
MC_REGISTER_SECURITY_BOM_HI = 0x9BC,
MC_REGISTER_SECURITY_CFG3_0 = MC_REGISTER_SECURITY_BOM_HI,
MC_REGISTER_SMMU_TRANSLATION_ENABLE_4_0 = 0xB98
} MC_REGISTER;
uint32_t SECURITY_BOM_HI;
uint32_t _0x9C0[118];
uint32_t SMMU_TRANSLATION_ENABLE_4_0;
} mc_register_t;
volatile security_carveout_t *get_carveout_by_id(unsigned int carveout);
void configure_default_carveouts(void);