Update CpuTestSimdReg.cs
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LDj3SNuD
GitHub
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commit
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1 changed files with 357 additions and 8 deletions
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@ -26,6 +26,20 @@ namespace Ryujinx.Tests.Cpu
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _4H2S1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8B_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8B4H2S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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@ -42,14 +56,6 @@ namespace Ryujinx.Tests.Cpu
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0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _4H2S1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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#endregion
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[Test, Description("ADD <V><d>, <V><n>, <V><m>")]
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@ -231,6 +237,349 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[Test, Description("AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void And_V_8B([ValueSource("_8B_")] [Random(1)] ulong A,
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[ValueSource("_8B_")] [Random(1)] ulong B)
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{
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uint Opcode = 0x0E221C20; // AND V0.8B, V1.8B, V2.8B
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
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AVec V1 = new AVec { X0 = A };
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AVec V2 = new AVec { X0 = B };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.V(1, new Bits(A));
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AArch64.V(2, new Bits(B));
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SimdFp.And_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.Zero);
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}
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[Test, Pairwise, Description("AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void And_V_16B([ValueSource("_8B_")] [Random(1)] ulong A0,
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[ValueSource("_8B_")] [Random(1)] ulong A1,
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[ValueSource("_8B_")] [Random(1)] ulong B0,
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[ValueSource("_8B_")] [Random(1)] ulong B1)
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{
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uint Opcode = 0x4E221C20; // AND V0.16B, V1.16B, V2.16B
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Bits Op = new Bits(Opcode);
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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AVec V2 = new AVec { X0 = B0, X1 = B1 };
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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AArch64.Vpart(2, 0, new Bits(B0));
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AArch64.Vpart(2, 1, new Bits(B1));
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SimdFp.And_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void Bic_V_8B([ValueSource("_8B_")] [Random(1)] ulong A,
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[ValueSource("_8B_")] [Random(1)] ulong B)
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{
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uint Opcode = 0x0E621C20; // BIC V0.8B, V1.8B, V2.8B
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
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AVec V1 = new AVec { X0 = A };
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AVec V2 = new AVec { X0 = B };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.V(1, new Bits(A));
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AArch64.V(2, new Bits(B));
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SimdFp.Bic_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.Zero);
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}
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[Test, Pairwise, Description("BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void Bic_V_16B([ValueSource("_8B_")] [Random(1)] ulong A0,
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[ValueSource("_8B_")] [Random(1)] ulong A1,
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[ValueSource("_8B_")] [Random(1)] ulong B0,
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[ValueSource("_8B_")] [Random(1)] ulong B1)
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{
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uint Opcode = 0x4E621C20; // BIC V0.16B, V1.16B, V2.16B
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Bits Op = new Bits(Opcode);
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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AVec V2 = new AVec { X0 = B0, X1 = B1 };
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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AArch64.Vpart(2, 0, new Bits(B0));
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AArch64.Vpart(2, 1, new Bits(B1));
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SimdFp.Bic_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void Bif_V_8B([ValueSource("_8B_")] [Random(1)] ulong _Z,
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[ValueSource("_8B_")] [Random(1)] ulong A,
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[ValueSource("_8B_")] [Random(1)] ulong B)
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{
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uint Opcode = 0x2EE21C20; // BIF V0.8B, V1.8B, V2.8B
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X0 = _Z, X1 = TestContext.CurrentContext.Random.NextULong() };
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AVec V1 = new AVec { X0 = A };
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AVec V2 = new AVec { X0 = B };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.Vpart(0, 0, new Bits(_Z));
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AArch64.V(1, new Bits(A));
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AArch64.V(2, new Bits(B));
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SimdFp.Bif_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.Zero);
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}
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[Test, Pairwise, Description("BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void Bif_V_16B([ValueSource("_8B_")] [Random(1)] ulong _Z0,
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[ValueSource("_8B_")] [Random(1)] ulong _Z1,
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[ValueSource("_8B_")] [Random(1)] ulong A0,
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[ValueSource("_8B_")] [Random(1)] ulong A1,
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[ValueSource("_8B_")] [Random(1)] ulong B0,
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[ValueSource("_8B_")] [Random(1)] ulong B1)
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{
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uint Opcode = 0x6EE21C20; // BIF V0.16B, V1.16B, V2.16B
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X0 = _Z0, X1 = _Z1 };
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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AVec V2 = new AVec { X0 = B0, X1 = B1 };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.Vpart(0, 0, new Bits(_Z0));
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AArch64.Vpart(0, 1, new Bits(_Z1));
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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AArch64.Vpart(2, 0, new Bits(B0));
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AArch64.Vpart(2, 1, new Bits(B1));
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SimdFp.Bif_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void Bit_V_8B([ValueSource("_8B_")] [Random(1)] ulong _Z,
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[ValueSource("_8B_")] [Random(1)] ulong A,
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[ValueSource("_8B_")] [Random(1)] ulong B)
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{
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uint Opcode = 0x2EA21C20; // BIT V0.8B, V1.8B, V2.8B
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X0 = _Z, X1 = TestContext.CurrentContext.Random.NextULong() };
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AVec V1 = new AVec { X0 = A };
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AVec V2 = new AVec { X0 = B };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.Vpart(0, 0, new Bits(_Z));
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AArch64.V(1, new Bits(A));
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AArch64.V(2, new Bits(B));
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SimdFp.Bit_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.Zero);
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}
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[Test, Pairwise, Description("BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void Bit_V_16B([ValueSource("_8B_")] [Random(1)] ulong _Z0,
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[ValueSource("_8B_")] [Random(1)] ulong _Z1,
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[ValueSource("_8B_")] [Random(1)] ulong A0,
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[ValueSource("_8B_")] [Random(1)] ulong A1,
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[ValueSource("_8B_")] [Random(1)] ulong B0,
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[ValueSource("_8B_")] [Random(1)] ulong B1)
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{
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uint Opcode = 0x6EA21C20; // BIT V0.16B, V1.16B, V2.16B
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X0 = _Z0, X1 = _Z1 };
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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AVec V2 = new AVec { X0 = B0, X1 = B1 };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.Vpart(0, 0, new Bits(_Z0));
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AArch64.Vpart(0, 1, new Bits(_Z1));
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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AArch64.Vpart(2, 0, new Bits(B0));
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AArch64.Vpart(2, 1, new Bits(B1));
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SimdFp.Bit_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void Bsl_V_8B([ValueSource("_8B_")] [Random(1)] ulong _Z,
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[ValueSource("_8B_")] [Random(1)] ulong A,
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[ValueSource("_8B_")] [Random(1)] ulong B)
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{
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uint Opcode = 0x2E621C20; // BSL V0.8B, V1.8B, V2.8B
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X0 = _Z, X1 = TestContext.CurrentContext.Random.NextULong() };
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AVec V1 = new AVec { X0 = A };
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AVec V2 = new AVec { X0 = B };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.Vpart(0, 0, new Bits(_Z));
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AArch64.V(1, new Bits(A));
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AArch64.V(2, new Bits(B));
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SimdFp.Bsl_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.Zero);
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}
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[Test, Pairwise, Description("BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void Bsl_V_16B([ValueSource("_8B_")] [Random(1)] ulong _Z0,
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[ValueSource("_8B_")] [Random(1)] ulong _Z1,
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[ValueSource("_8B_")] [Random(1)] ulong A0,
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[ValueSource("_8B_")] [Random(1)] ulong A1,
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[ValueSource("_8B_")] [Random(1)] ulong B0,
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[ValueSource("_8B_")] [Random(1)] ulong B1)
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{
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uint Opcode = 0x6E621C20; // BSL V0.16B, V1.16B, V2.16B
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X0 = _Z0, X1 = _Z1 };
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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AVec V2 = new AVec { X0 = B0, X1 = B1 };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.Vpart(0, 0, new Bits(_Z0));
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AArch64.Vpart(0, 1, new Bits(_Z1));
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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AArch64.Vpart(2, 0, new Bits(B0));
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AArch64.Vpart(2, 1, new Bits(B1));
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SimdFp.Bsl_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void Orn_V_8B([ValueSource("_8B_")] [Random(1)] ulong A,
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[ValueSource("_8B_")] [Random(1)] ulong B)
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{
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uint Opcode = 0x0EE21C20; // ORN V0.8B, V1.8B, V2.8B
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
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AVec V1 = new AVec { X0 = A };
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AVec V2 = new AVec { X0 = B };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.V(1, new Bits(A));
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AArch64.V(2, new Bits(B));
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SimdFp.Orn_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.Zero);
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}
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[Test, Pairwise, Description("ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void Orn_V_16B([ValueSource("_8B_")] [Random(1)] ulong A0,
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[ValueSource("_8B_")] [Random(1)] ulong A1,
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[ValueSource("_8B_")] [Random(1)] ulong B0,
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[ValueSource("_8B_")] [Random(1)] ulong B1)
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{
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uint Opcode = 0x4EE21C20; // ORN V0.16B, V1.16B, V2.16B
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Bits Op = new Bits(Opcode);
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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AVec V2 = new AVec { X0 = B0, X1 = B1 };
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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AArch64.Vpart(2, 0, new Bits(B0));
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AArch64.Vpart(2, 1, new Bits(B1));
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SimdFp.Orn_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Orr_V_8B([ValueSource("_8B_")] [Random(1)] ulong A,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B)
|
||||
{
|
||||
uint Opcode = 0x0EA21C20; // ORR V0.8B, V1.8B, V2.8B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
SimdFp.Orr_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Orr_V_16B([ValueSource("_8B_")] [Random(1)] ulong A0,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong A1,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B0,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B1)
|
||||
{
|
||||
uint Opcode = 0x4EA21C20; // ORR V0.16B, V1.16B, V2.16B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
AArch64.Vpart(1, 1, new Bits(A1));
|
||||
AArch64.Vpart(2, 0, new Bits(B0));
|
||||
AArch64.Vpart(2, 1, new Bits(B1));
|
||||
SimdFp.Orr_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("RADDHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
|
||||
public void Raddhn_V_8H8B_4S4H_2D2S([ValueSource("_4H2S1D_")] [Random(1)] ulong A0,
|
||||
[ValueSource("_4H2S1D_")] [Random(1)] ulong A1,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue