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Rename Cond -> Condition

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This commit is contained in:
gdkchan 2019-01-22 21:32:37 -02:00
commit 0acdbe7a6d
13 changed files with 33 additions and 33 deletions
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2
ChocolArm64/Decoders/Cond.cs → ChocolArm64/Decoders/Condition.cs
View file

@ -1,6 +1,6 @@
namespace ChocolArm64.Decoders
{
enum Cond
enum Condition
{
Eq = 0,
Ne = 1,

2
ChocolArm64/Decoders/Decoder.cs
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@ -161,7 +161,7 @@ namespace ChocolArm64.Decoders
//Note: On ARM32, most instructions have conditional execution,
//so there's no "Always" (unconditional) branch like on ARM64.
//We need to check if the condition is "Always" instead.
return IsAarch32Branch(op) && op.Cond >= Cond.Al;
return IsAarch32Branch(op) && op.Cond >= Condition.Al;
}
private static bool IsAarch32Branch(OpCode64 opCode)

2
ChocolArm64/Decoders/IOpCode32.cs
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@ -2,7 +2,7 @@ namespace ChocolArm64.Decoders
{
interface IOpCode32 : IOpCode64
{
Cond Cond { get; }
Condition Cond { get; }
uint GetPc();
}

2
ChocolArm64/Decoders/IOpCodeCond64.cs
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@ -2,6 +2,6 @@ namespace ChocolArm64.Decoders
{
interface IOpCodeCond64 : IOpCode64
{
Cond Cond { get; }
Condition Cond { get; }
}
}

4
ChocolArm64/Decoders/OpCode32.cs
View file

@ -5,13 +5,13 @@ namespace ChocolArm64.Decoders
{
class OpCode32 : OpCode64
{
public Cond Cond { get; protected set; }
public Condition Cond { get; protected set; }
public OpCode32(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
RegisterSize = RegisterSize.Int32;
Cond = (Cond)((uint)opCode >> 28);
Cond = (Condition)((uint)opCode >> 28);
}
public uint GetPc()

4
ChocolArm64/Decoders/OpCodeBImm32.cs
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@ -11,14 +11,14 @@ namespace ChocolArm64.Decoders
uint pc = GetPc();
//When the codition is never, the instruction is BLX to Thumb mode.
if (Cond != Cond.Nv)
if (Cond != Condition.Nv)
{
pc &= ~3u;
}
Imm = pc + DecoderHelper.DecodeImm24_2(opCode);
if (Cond == Cond.Nv)
if (Cond == Condition.Nv)
{
long H = (opCode >> 23) & 2;

4
ChocolArm64/Decoders/OpCodeBImmCond64.cs
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@ -4,7 +4,7 @@ namespace ChocolArm64.Decoders
{
class OpCodeBImmCond64 : OpCodeBImm64, IOpCodeCond64
{
public Cond Cond { get; private set; }
public Condition Cond { get; private set; }
public OpCodeBImmCond64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
@ -17,7 +17,7 @@ namespace ChocolArm64.Decoders
return;
}
Cond = (Cond)(opCode & 0xf);
Cond = (Condition)(opCode & 0xf);
Imm = position + DecoderHelper.DecodeImmS19_2(opCode);
}

4
ChocolArm64/Decoders/OpCodeCcmp64.cs
View file

@ -8,7 +8,7 @@ namespace ChocolArm64.Decoders
public int Nzcv { get; private set; }
protected int RmImm;
public Cond Cond { get; private set; }
public Condition Cond { get; private set; }
public OpCodeCcmp64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
@ -22,7 +22,7 @@ namespace ChocolArm64.Decoders
}
Nzcv = (opCode >> 0) & 0xf;
Cond = (Cond)((opCode >> 12) & 0xf);
Cond = (Condition)((opCode >> 12) & 0xf);
RmImm = (opCode >> 16) & 0x1f;
Rd = RegisterAlias.Zr;

4
ChocolArm64/Decoders/OpCodeCsel64.cs
View file

@ -6,12 +6,12 @@ namespace ChocolArm64.Decoders
{
public int Rm { get; private set; }
public Cond Cond { get; private set; }
public Condition Cond { get; private set; }
public OpCodeCsel64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rm = (opCode >> 16) & 0x1f;
Cond = (Cond)((opCode >> 12) & 0xf);
Cond = (Condition)((opCode >> 12) & 0xf);
}
}
}

4
ChocolArm64/Decoders/OpCodeSimdFcond64.cs
View file

@ -6,12 +6,12 @@ namespace ChocolArm64.Decoders
{
public int Nzcv { get; private set; }
public Cond Cond { get; private set; }
public Condition Cond { get; private set; }
public OpCodeSimdFcond64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Nzcv = (opCode >> 0) & 0xf;
Cond = (Cond)((opCode >> 12) & 0xf);
Cond = (Condition)((opCode >> 12) & 0xf);
}
}
}

2
ChocolArm64/Decoders/OpCodeT16.cs
View file

@ -6,7 +6,7 @@ namespace ChocolArm64.Decoders
{
public OpCodeT16(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Cond = Cond.Al;
Cond = Condition.Al;
OpCodeSizeInBytes = 2;
}

2
ChocolArm64/Instructions/InstEmitFlow.cs
View file

@ -102,7 +102,7 @@ namespace ChocolArm64.Instructions
EmitBranch(context, ilOp);
}
private static void EmitBranch(ILEmitterCtx context, Cond cond)
private static void EmitBranch(ILEmitterCtx context, Condition cond)
{
OpCodeBImm64 op = (OpCodeBImm64)context.CurrOp;

30
ChocolArm64/Translation/ILEmitterCtx.cs
View file

@ -108,7 +108,7 @@ namespace ChocolArm64.Translation
//used by some unconditional instructions.
ILLabel lblSkip = null;
if (CurrOp is OpCode32 op && op.Cond < Cond.Al)
if (CurrOp is OpCode32 op && op.Cond < Condition.Al)
{
lblSkip = new ILLabel();
@ -138,11 +138,11 @@ namespace ChocolArm64.Translation
_ilBlock.Add(new ILBarrier());
}
private Cond GetInverseCond(Cond cond)
private Condition GetInverseCond(Condition cond)
{
//Bit 0 of all conditions is basically a negation bit, so
//inverting this bit has the effect of inverting the condition.
return (Cond)((int)cond ^ 1);
return (Condition)((int)cond ^ 1);
}
private void EmitSynchronization()
@ -292,21 +292,21 @@ namespace ChocolArm64.Translation
Stloc(CmpOptTmp1Index, IoType.Int);
}
private Dictionary<Cond, OpCode> _branchOps = new Dictionary<Cond, OpCode>()
private Dictionary<Condition, OpCode> _branchOps = new Dictionary<Condition, OpCode>()
{
{ Cond.Eq, OpCodes.Beq },
{ Cond.Ne, OpCodes.Bne_Un },
{ Cond.GeUn, OpCodes.Bge_Un },
{ Cond.LtUn, OpCodes.Blt_Un },
{ Cond.GtUn, OpCodes.Bgt_Un },
{ Cond.LeUn, OpCodes.Ble_Un },
{ Cond.Ge, OpCodes.Bge },
{ Cond.Lt, OpCodes.Blt },
{ Cond.Gt, OpCodes.Bgt },
{ Cond.Le, OpCodes.Ble }
{ Condition.Eq, OpCodes.Beq },
{ Condition.Ne, OpCodes.Bne_Un },
{ Condition.GeUn, OpCodes.Bge_Un },
{ Condition.LtUn, OpCodes.Blt_Un },
{ Condition.GtUn, OpCodes.Bgt_Un },
{ Condition.LeUn, OpCodes.Ble_Un },
{ Condition.Ge, OpCodes.Bge },
{ Condition.Lt, OpCodes.Blt },
{ Condition.Gt, OpCodes.Bgt },
{ Condition.Le, OpCodes.Ble }
};
public void EmitCondBranch(ILLabel target, Cond cond)
public void EmitCondBranch(ILLabel target, Condition cond)
{
OpCode ilOp;