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Add Fcsel_S Test.

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LDj3SNuD 2019-06-25 01:45:00 +02:00 • committed by GitHub
parent 66f279c169
commit 43f48c2f41
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58
Ryujinx.Tests/Cpu/CpuTestSimdFcond.cs
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@ -115,6 +115,22 @@ namespace Ryujinx.Tests.Cpu
0x1E620430u // FCCMPE D1, D2, #0, EQ
};
}
private static uint[] _F_Csel_S_S_()
{
return new uint[]
{
0x1E220C20u // FCSEL S0, S1, S2, EQ
};
}
private static uint[] _F_Csel_S_D_()
{
return new uint[]
{
0x1E620C20u // FCSEL D0, D1, D2, EQ
};
}
#endregion
private const int RndCnt = 2;
@ -173,6 +189,48 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc);
}
[Test, Pairwise] [Explicit]
public void F_Csel_S_S([ValueSource("_F_Csel_S_S_")] uint opcodes,
[ValueSource("_1S_F_")] ulong a,
[ValueSource("_1S_F_")] ulong b,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
0b1100u, 0b1101u, 0b1110u, 0b1111u)] uint cond) // GT, LE, AL, NV>
{
opcodes |= ((cond & 15) << 12);
ulong z = TestContext.CurrentContext.Random.NextULong();
Vector128<float> v0 = MakeVectorE0E1(z, z);
Vector128<float> v1 = MakeVectorE0(a);
Vector128<float> v2 = MakeVectorE0(b);
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void F_Csel_S_D([ValueSource("_F_Csel_S_D_")] uint opcodes,
[ValueSource("_1D_F_")] ulong a,
[ValueSource("_1D_F_")] ulong b,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
0b1100u, 0b1101u, 0b1110u, 0b1111u)] uint cond) // GT, LE, AL, NV>
{
opcodes |= ((cond & 15) << 12);
ulong z = TestContext.CurrentContext.Random.NextULong();
Vector128<float> v0 = MakeVectorE1(z);
Vector128<float> v1 = MakeVectorE0(a);
Vector128<float> v2 = MakeVectorE0(b);
SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
CompareAgainstUnicorn();
}
#endif
}
}