Add Fcsel_S Test.
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@ -115,6 +115,22 @@ namespace Ryujinx.Tests.Cpu
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0x1E620430u // FCCMPE D1, D2, #0, EQ
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0x1E620430u // FCCMPE D1, D2, #0, EQ
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};
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};
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}
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}
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private static uint[] _F_Csel_S_S_()
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{
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return new uint[]
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{
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0x1E220C20u // FCSEL S0, S1, S2, EQ
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};
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}
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private static uint[] _F_Csel_S_D_()
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{
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return new uint[]
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{
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0x1E620C20u // FCSEL D0, D1, D2, EQ
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};
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}
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#endregion
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#endregion
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private const int RndCnt = 2;
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private const int RndCnt = 2;
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@ -173,6 +189,48 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc);
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CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc);
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}
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}
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[Test, Pairwise] [Explicit]
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public void F_Csel_S_S([ValueSource("_F_Csel_S_S_")] uint opcodes,
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[ValueSource("_1S_F_")] ulong a,
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[ValueSource("_1S_F_")] ulong b,
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u, 0b1110u, 0b1111u)] uint cond) // GT, LE, AL, NV>
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{
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opcodes |= ((cond & 15) << 12);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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Vector128<float> v1 = MakeVectorE0(a);
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Vector128<float> v2 = MakeVectorE0(b);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise] [Explicit]
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public void F_Csel_S_D([ValueSource("_F_Csel_S_D_")] uint opcodes,
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[ValueSource("_1D_F_")] ulong a,
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[ValueSource("_1D_F_")] ulong b,
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u, 0b1110u, 0b1111u)] uint cond) // GT, LE, AL, NV>
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{
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opcodes |= ((cond & 15) << 12);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> v0 = MakeVectorE1(z);
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Vector128<float> v1 = MakeVectorE0(a);
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Vector128<float> v2 = MakeVectorE0(b);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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#endif
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#endif
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}
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}
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}
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}
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