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Update AInstEmitSimdShift.cs

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LDj3SNuD 2018-10-13 01:09:32 +02:00 • committed by GitHub
commit 4abff91426
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1 changed files with 72 additions and 6 deletions
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66
ChocolArm64/Instruction/AInstEmitSimdShift.cs
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@ -3,6 +3,7 @@ using ChocolArm64.State;
using ChocolArm64.Translation; using ChocolArm64.Translation;
using System; using System;
using System.Reflection.Emit; using System.Reflection.Emit;
using System.Runtime.Intrinsics.X86;
using static ChocolArm64.Instruction.AInstEmitSimdHelper; using static ChocolArm64.Instruction.AInstEmitSimdHelper;
@ -31,6 +32,25 @@ namespace ChocolArm64.Instruction
{ {
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp; AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
if (AOptimizations.UseSse2 && Op.Size > 0)
{
Type[] Types = new Type[] { VectorUIntTypesPerSizeLog2[Op.Size], typeof(byte) };
EmitLdvecWithUnsignedCast(Context, Op.Rn, Op.Size);
Context.EmitLdc_I4(GetImmShl(Op));
Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftLeftLogical), Types));
EmitStvecWithUnsignedCast(Context, Op.Rd, Op.Size);
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
else
{
EmitVectorUnaryOpZx(Context, () => EmitVectorUnaryOpZx(Context, () =>
{ {
Context.EmitLdc_I4(GetImmShl(Op)); Context.EmitLdc_I4(GetImmShl(Op));
@ -38,6 +58,7 @@ namespace ChocolArm64.Instruction
Context.Emit(OpCodes.Shl); Context.Emit(OpCodes.Shl);
}); });
} }
}
public static void Shll_V(AILEmitterCtx Context) public static void Shll_V(AILEmitterCtx Context)
{ {
@ -166,9 +187,32 @@ namespace ChocolArm64.Instruction
} }
public static void Sshr_V(AILEmitterCtx Context) public static void Sshr_V(AILEmitterCtx Context)
{
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
if (AOptimizations.UseSse2 && Op.Size > 0
&& Op.Size < 3)
{
Type[] Types = new Type[] { VectorIntTypesPerSizeLog2[Op.Size], typeof(byte) };
EmitLdvecWithSignedCast(Context, Op.Rn, Op.Size);
Context.EmitLdc_I4(GetImmShr(Op));
Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightArithmetic), Types));
EmitStvecWithSignedCast(Context, Op.Rd, Op.Size);
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
else
{ {
EmitShrImmOp(Context, ShrImmFlags.VectorSx); EmitShrImmOp(Context, ShrImmFlags.VectorSx);
} }
}
public static void Ssra_S(AILEmitterCtx Context) public static void Ssra_S(AILEmitterCtx Context)
{ {
@ -238,9 +282,31 @@ namespace ChocolArm64.Instruction
} }
public static void Ushr_V(AILEmitterCtx Context) public static void Ushr_V(AILEmitterCtx Context)
{
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
if (AOptimizations.UseSse2 && Op.Size > 0)
{
Type[] Types = new Type[] { VectorUIntTypesPerSizeLog2[Op.Size], typeof(byte) };
EmitLdvecWithUnsignedCast(Context, Op.Rn, Op.Size);
Context.EmitLdc_I4(GetImmShr(Op));
Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical), Types));
EmitStvecWithUnsignedCast(Context, Op.Rd, Op.Size);
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
else
{ {
EmitShrImmOp(Context, ShrImmFlags.VectorZx); EmitShrImmOp(Context, ShrImmFlags.VectorZx);
} }
}
public static void Usra_S(AILEmitterCtx Context) public static void Usra_S(AILEmitterCtx Context)
{ {