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Address LDj feedback (minus table flatten)

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one final look before it's all gone. the world is so beautiful.
This commit is contained in:
riperiperi 2020-02-19 22:50:40 +00:00
commit 520b20fe34
9 changed files with 24 additions and 22 deletions
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8
ARMeilleure/Decoders/OpCodeTable.cs
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@ -818,10 +818,10 @@ namespace ARMeilleure.Decoders
SetA32("1111001x0x<<xxxxxxxx0110xxx1xxxx", InstName.Vmin, InstEmit32.Vmin_I, typeof(OpCode32SimdReg)); SetA32("1111001x0x<<xxxxxxxx0110xxx1xxxx", InstName.Vmin, InstEmit32.Vmin_I, typeof(OpCode32SimdReg));
SetA32("111100100x10xxxxxxxx1111xxx0xxxx", InstName.Vmin, InstEmit32.Vmin_V, typeof(OpCode32SimdReg)); SetA32("111100100x10xxxxxxxx1111xxx0xxxx", InstName.Vmin, InstEmit32.Vmin_V, typeof(OpCode32SimdReg));
SetA32("111111101x00xxxxxxxx10>>x0x0xxxx", InstName.Vmaxnm, InstEmit32.VmaxNm_S, typeof(OpCode32SimdRegS)); SetA32("111111101x00xxxxxxxx10>>x0x0xxxx", InstName.Vmaxnm, InstEmit32.Vmaxnm_S, typeof(OpCode32SimdRegS));
SetA32("111100110x0xxxxxxxxx1111xxx1xxxx", InstName.Vmaxnm, InstEmit32.VmaxminNm_V, typeof(OpCode32SimdReg)); SetA32("111100110x0xxxxxxxxx1111xxx1xxxx", InstName.Vmaxnm, InstEmit32.Vmaxnm_V, typeof(OpCode32SimdReg));
SetA32("111111101x00xxxxxxxx10>>x1x0xxxx", InstName.Vminnm, InstEmit32.VminNm_S, typeof(OpCode32SimdRegS)); SetA32("111111101x00xxxxxxxx10>>x1x0xxxx", InstName.Vminnm, InstEmit32.Vminnm_S, typeof(OpCode32SimdRegS));
SetA32("111100110x1xxxxxxxxx1111xxx1xxxx", InstName.Vminnm, InstEmit32.VmaxminNm_V, typeof(OpCode32SimdReg)); SetA32("111100110x1xxxxxxxxx1111xxx1xxxx", InstName.Vminnm, InstEmit32.Vminnm_V, typeof(OpCode32SimdReg));
SetA32("111100100xxxxxxxxxxx1001xxx0xxxx", InstName.Vmla, InstEmit32.Vmla_I, typeof(OpCode32SimdReg)); SetA32("111100100xxxxxxxxxxx1001xxx0xxxx", InstName.Vmla, InstEmit32.Vmla_I, typeof(OpCode32SimdReg));
SetA32("<<<<11100x00xxxxxxxx101xx0x0xxxx", InstName.Vmla, InstEmit32.Vmla_S, typeof(OpCode32SimdRegS)); SetA32("<<<<11100x00xxxxxxxx101xx0x0xxxx", InstName.Vmla, InstEmit32.Vmla_S, typeof(OpCode32SimdRegS));

18
ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs
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@ -238,24 +238,24 @@ namespace ARMeilleure.Instructions
} }
} }
public static void VmaxNm_S(ArmEmitterContext context) public static void Vmaxnm_S(ArmEmitterContext context)
{ {
EmitScalarBinaryOpF32(context, (op1, op2) => EmitSoftFloatCall(context, SoftFloat32.FPMaxNum, SoftFloat64.FPMaxNum, op1, op2)); EmitScalarBinaryOpF32(context, (op1, op2) => EmitSoftFloatCall(context, SoftFloat32.FPMaxNum, SoftFloat64.FPMaxNum, op1, op2));
} }
public static void VminNm_S(ArmEmitterContext context) public static void Vmaxnm_V(ArmEmitterContext context)
{
EmitVectorBinaryOpSx32(context, (op1, op2) => EmitSoftFloatCallDefaultFpscr(context, SoftFloat32.FPMaxNumFpscr, SoftFloat64.FPMaxNumFpscr, op1, op2));
}
public static void Vminnm_S(ArmEmitterContext context)
{ {
EmitScalarBinaryOpF32(context, (op1, op2) => EmitSoftFloatCall(context, SoftFloat32.FPMinNum, SoftFloat64.FPMinNum, op1, op2)); EmitScalarBinaryOpF32(context, (op1, op2) => EmitSoftFloatCall(context, SoftFloat32.FPMinNum, SoftFloat64.FPMinNum, op1, op2));
} }
public static void VmaxminNm_V(ArmEmitterContext context) public static void Vminnm_V(ArmEmitterContext context)
{ {
OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp; EmitVectorBinaryOpSx32(context, (op1, op2) => EmitSoftFloatCallDefaultFpscr(context, SoftFloat32.FPMinNumFpscr, SoftFloat64.FPMinNumFpscr, op1, op2));
bool max = (op.Size & 2) == 0; // Op is high bit of size (not used for fp).
_F32_F32_F32_Bool f32 = max ? new _F32_F32_F32_Bool(SoftFloat32.FPMaxNumFpscr) : new _F32_F32_F32_Bool(SoftFloat32.FPMinNumFpscr);
_F64_F64_F64_Bool f64 = max ? new _F64_F64_F64_Bool(SoftFloat64.FPMaxNumFpscr) : new _F64_F64_F64_Bool(SoftFloat64.FPMinNumFpscr);
EmitVectorBinaryOpSx32(context, (op1, op2) => EmitSoftFloatCallDefaultFpscr(context, f32, f64, op1, op2));
} }
public static void Vmax_V(ArmEmitterContext context) public static void Vmax_V(ArmEmitterContext context)

1
ARMeilleure/Instructions/SoftFloat.cs
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@ -2799,6 +2799,7 @@ namespace ARMeilleure.Instructions
{ {
bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
if (inf1 && inf2 && sign1 == sign2) if (inf1 && inf2 && sign1 == sign2)
{ {
result = FPDefaultNaN(); result = FPDefaultNaN();

1
Ryujinx.Tests/Cpu/CpuTestAlu32.cs
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@ -9,6 +9,7 @@ namespace Ryujinx.Tests.Cpu
public sealed class CpuTestAlu32 : CpuTest32 public sealed class CpuTestAlu32 : CpuTest32
{ {
#if Alu32 #if Alu32
#region "ValueSource (Opcodes)" #region "ValueSource (Opcodes)"
private static uint[] _Lsr_Lsl_Asr_Ror_() private static uint[] _Lsr_Lsl_Asr_Ror_()
{ {

3
Ryujinx.Tests/Cpu/CpuTestAluRs32.cs
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@ -8,6 +8,7 @@ namespace Ryujinx.Tests.Cpu
public sealed class CpuTestAluRs32 : CpuTest32 public sealed class CpuTestAluRs32 : CpuTest32
{ {
#if AluRs32 #if AluRs32
#region "ValueSource (Opcodes)" #region "ValueSource (Opcodes)"
private static uint[] _Add_Adds_Rsb_Rsbs_() private static uint[] _Add_Adds_Rsb_Rsbs_()
{ {
@ -32,7 +33,7 @@ namespace Ryujinx.Tests.Cpu
0xe0d00000u // SBCS R0, R0, R0 0xe0d00000u // SBCS R0, R0, R0
}; };
} }
#endregion #endregion
private const int RndCnt = 2; private const int RndCnt = 2;
private const int RndCntAmount = 2; private const int RndCntAmount = 2;

1
Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
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@ -10,6 +10,7 @@ namespace Ryujinx.Tests.Cpu
public sealed class CpuTestSimdLogical32 : CpuTest32 public sealed class CpuTestSimdLogical32 : CpuTest32
{ {
#if SimdLogical32 #if SimdLogical32
#region "ValueSource (Opcodes)" #region "ValueSource (Opcodes)"
private static uint[] _Vbif_Vbit_Vbsl_Vand_() private static uint[] _Vbif_Vbit_Vbsl_Vand_()
{ {

4
Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs
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@ -3,8 +3,6 @@
using ARMeilleure.State; using ARMeilleure.State;
using NUnit.Framework; using NUnit.Framework;
using System; using System;
using System.Collections.Generic;
using System.Text;
namespace Ryujinx.Tests.Cpu namespace Ryujinx.Tests.Cpu
{ {
@ -12,7 +10,7 @@ namespace Ryujinx.Tests.Cpu
public sealed class CpuTestSimdMov32 : CpuTest32 public sealed class CpuTestSimdMov32 : CpuTest32
{ {
#if SimdMov32 #if SimdMov32
private const int RndCntImm = 10; private const int RndCntImm = 2;
[Test, Pairwise, Description("VMOV.I<size> <Dd/Qd>, #<imm>")] [Test, Pairwise, Description("VMOV.I<size> <Dd/Qd>, #<imm>")]
public void Movi_V([Range(0u, 10u)] uint variant, public void Movi_V([Range(0u, 10u)] uint variant,

8
Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs
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@ -8,11 +8,11 @@ using System.Collections.Generic;
namespace Ryujinx.Tests.Cpu namespace Ryujinx.Tests.Cpu
{ {
[Category("SimdReg32")] [Category("SimdReg32")]
public sealed class CpuTestSimdReg32 : CpuTest32 public sealed class CpuTestSimdReg32 : CpuTest32
{ {
#if SimdReg32 #if SimdReg32
#region "ValueSource (Types)" #region "ValueSource (Types)"
private static ulong[] _1B1H1S1D_() private static ulong[] _1B1H1S1D_()
{ {
return new ulong[] { 0x0000000000000000ul, 0x000000000000007Ful, return new ulong[] { 0x0000000000000000ul, 0x000000000000007Ful,
@ -199,9 +199,9 @@ namespace Ryujinx.Tests.Cpu
yield return rnd2; yield return rnd2;
} }
} }
#endregion #endregion
private const int RndCnt = 5; private const int RndCnt = 2;
private static readonly bool NoZeros = false; private static readonly bool NoZeros = false;
private static readonly bool NoInfs = false; private static readonly bool NoInfs = false;

2
Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs
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@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
public sealed class CpuTestSimdShImm32 : CpuTest32 public sealed class CpuTestSimdShImm32 : CpuTest32
{ {
#if SimdShImm32 #if SimdShImm32
private const int RndCnt = 5; private const int RndCnt = 2;
[Test, Pairwise, Description("VSHL.<size> {<Vd>}, <Vm>, #<imm>")] [Test, Pairwise, Description("VSHL.<size> {<Vd>}, <Vm>, #<imm>")]
public void Vshl_Imm([Values(0u)] uint rd, public void Vshl_Imm([Values(0u)] uint rd,