add ASRV test
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3 changed files with 73 additions and 37 deletions
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@ -27,11 +27,14 @@ namespace Ryujinx.Tests.Cpu
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{
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//ADCS (X0/W0), (X1, W1), (X2/W2)
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AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B, Carry: CarryState);
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Assert.AreEqual(Negative, ThreadState.Negative);
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Assert.IsFalse(ThreadState.Overflow);
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Assert.AreEqual(Zero, ThreadState.Zero);
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Assert.AreEqual(Carry, ThreadState.Carry);
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Assert.AreEqual(Result, ThreadState.X0);
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Assert.Multiple(() =>
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{
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Assert.IsFalse(ThreadState.Overflow);
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Assert.AreEqual(Negative, ThreadState.Negative);
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Assert.AreEqual(Zero, ThreadState.Zero);
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Assert.AreEqual(Carry, ThreadState.Carry);
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Assert.AreEqual(Result, ThreadState.X0);
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});
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}
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[Test]
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@ -51,11 +54,14 @@ namespace Ryujinx.Tests.Cpu
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{
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//ADDS WZR, WSP, #5
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AThreadState ThreadState = SingleOpcode(0x310017FF, X31: A);
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Assert.IsFalse(ThreadState.Negative);
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Assert.AreEqual(Zero, ThreadState.Zero);
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Assert.AreEqual(Carry, ThreadState.Carry);
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Assert.IsFalse(ThreadState.Overflow);
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Assert.AreEqual(A, ThreadState.X31);
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Assert.Multiple(() =>
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{
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Assert.IsFalse(ThreadState.Negative);
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Assert.IsFalse(ThreadState.Overflow);
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Assert.AreEqual(Zero, ThreadState.Zero);
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Assert.AreEqual(Carry, ThreadState.Carry);
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Assert.AreEqual(A, ThreadState.X31);
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});
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}
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[TestCase(0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFul, true, false)]
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@ -66,26 +72,55 @@ namespace Ryujinx.Tests.Cpu
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// ANDS W0, W1, W2
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uint Opcode = 0x6A020020;
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AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B);
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Assert.AreEqual(Result, ThreadState.X0);
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Assert.AreEqual(Negative, ThreadState.Negative);
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Assert.AreEqual(Zero, ThreadState.Zero);
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Assert.Multiple(() =>
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{
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Assert.AreEqual(Result, ThreadState.X0);
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Assert.AreEqual(Negative, ThreadState.Negative);
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Assert.AreEqual(Zero, ThreadState.Zero);
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});
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}
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[Test]
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public void OrrBitmasks()
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[TestCase(0x0000FF44u, 0x00000004u, 0x00000FF4u)]
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[TestCase(0x00000000u, 0x00000004u, 0x00000000u)]
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[TestCase(0x0000FF44u, 0x00000008u, 0x000000FFu)]
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[TestCase(0xFFFFFFFFu, 0x00000004u, 0xFFFFFFFFu)]
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[TestCase(0xFFFFFFFFu, 0x00000008u, 0xFFFFFFFFu)]
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[TestCase(0xFFFFFFFFu, 0x00000020u, 0xFFFFFFFFu)]
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[TestCase(0x0FFFFFFFu, 0x0000001Cu, 0x00000000u)]
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[TestCase(0x80000000u, 0x0000001Fu, 0xFFFFFFFFu)]
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[TestCase(0xCAFE0000u, 0x00000020u, 0xCAFE0000u)]
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public void Asrv32(uint A, uint ShiftValue, uint Result)
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{
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// ORR W0, WZR, #0x01010101
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Assert.AreEqual(0x01010101, SingleOpcode(0x3200C3E0).X0);
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// ASRV W0, W1, W2
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AThreadState ThreadState = SingleOpcode(0x1AC22820, X1: A, X2: ShiftValue);
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Assert.AreEqual(Result, ThreadState.X0);
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}
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Reset();
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[TestCase(0x000000000000FF44ul, 0x00000004u, 0x0000000000000FF4ul)]
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[TestCase(0x0000000000000000ul, 0x00000004u, 0x0000000000000000ul)]
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[TestCase(0x000000000000FF44ul, 0x00000008u, 0x00000000000000FFul)]
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[TestCase(0x00000000FFFFFFFFul, 0x00000004u, 0x000000000FFFFFFFul)]
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[TestCase(0x00000000FFFFFFFFul, 0x00000008u, 0x0000000000FFFFFFul)]
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[TestCase(0x00000000FFFFFFFFul, 0x00000020u, 0x0000000000000000ul)]
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[TestCase(0x000000000FFFFFFFul, 0x0000001Cu, 0x0000000000000000ul)]
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[TestCase(0x000CC4488FFFFFFFul, 0x0000001Cu, 0x0000000000CC4488ul)]
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[TestCase(0xFFFFFFFFFFFFFFFFul, 0x0000001Cu, 0xFFFFFFFFFFFFFFFFul)]
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[TestCase(0x8000000000000000ul, 0x0000003Fu, 0xFFFFFFFFFFFFFFFFul)]
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[TestCase(0xCAFE000000000000ul, 0x00000040u, 0xCAFE000000000000ul)]
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public void Asrv64(ulong A, uint ShiftValue, ulong Result)
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{
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// ASRV X0, X1, X2
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AThreadState ThreadState = SingleOpcode(0x9AC22820, X1: A, X2: ShiftValue);
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Assert.AreEqual(Result, ThreadState.X0);
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}
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// ORR W1, WZR, #0x00F000F0
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Assert.AreEqual(0x00F000F0, SingleOpcode(0x320C8FE1).X1);
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Reset();
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// ORR W2, WZR, #1
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Assert.AreEqual(0x00000001, SingleOpcode(0x320003E2).X2);
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[TestCase(0x01010101u, 0x3200C3E2u)]
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[TestCase(0x00F000F0u, 0x320C8FE2u)]
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[TestCase(0x00000001u, 0x320003E2u)]
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public void OrrBitmasks(uint Bitmask, uint Opcode)
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{
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// ORR W2, WZR, #Bitmask
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Assert.AreEqual(Bitmask, SingleOpcode(Opcode).X2);
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}
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[Test]
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@ -114,11 +149,14 @@ namespace Ryujinx.Tests.Cpu
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{
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//SBCS (X0/W0), (X1, W1), (X2/W2)
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AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B, Carry: CarryState);
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Assert.AreEqual(Negative, ThreadState.Negative);
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Assert.IsFalse(ThreadState.Overflow);
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Assert.AreEqual(Zero, ThreadState.Zero);
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Assert.AreEqual(Carry, ThreadState.Carry);
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Assert.AreEqual(Result, ThreadState.X0);
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Assert.Multiple(() =>
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{
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Assert.IsFalse(ThreadState.Overflow);
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Assert.AreEqual(Negative, ThreadState.Negative);
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Assert.AreEqual(Zero, ThreadState.Zero);
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Assert.AreEqual(Carry, ThreadState.Carry);
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Assert.AreEqual(Result, ThreadState.X0);
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});
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}
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}
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}
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@ -197,8 +197,11 @@ namespace Ryujinx.Tests.Cpu
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Opcode(0xD4200000);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.AreEqual(0, GetThreadState().X0);
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Assert.IsTrue(GetThreadState().Zero);
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Assert.Multiple(() =>
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{
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Assert.AreEqual(0, GetThreadState().X0);
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Assert.IsTrue(GetThreadState().Zero);
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});
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}
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[Test]
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@ -13,7 +13,6 @@ namespace Ryujinx.Tests.Cpu
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[TestCase(0x40733333u, 'M', false, 0x40400000u)]
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[TestCase(0x3F99999Au, 'Z', false, 0x3F800000u)]
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[TestCase(0x3FE66666u, 'Z', false, 0x3F800000u)]
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//+/-0
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[TestCase(0x00000000u, 'N', false, 0x00000000u)]
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[TestCase(0x00000000u, 'P', false, 0x00000000u)]
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[TestCase(0x00000000u, 'M', false, 0x00000000u)]
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@ -22,17 +21,14 @@ namespace Ryujinx.Tests.Cpu
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[TestCase(0x80000000u, 'P', false, 0x80000000u)]
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[TestCase(0x80000000u, 'M', false, 0x80000000u)]
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[TestCase(0x80000000u, 'Z', false, 0x80000000u)]
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//+inf
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[TestCase(0x7F800000u, 'N', false, 0x7F800000u)]
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[TestCase(0x7F800000u, 'P', false, 0x7F800000u)]
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[TestCase(0x7F800000u, 'M', false, 0x7F800000u)]
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[TestCase(0x7F800000u, 'Z', false, 0x7F800000u)]
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//-inf
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[TestCase(0xFF800000u, 'N', false, 0xFF800000u)]
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[TestCase(0xFF800000u, 'P', false, 0xFF800000u)]
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[TestCase(0xFF800000u, 'M', false, 0xFF800000u)]
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[TestCase(0xFF800000u, 'Z', false, 0xFF800000u)]
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//SNaN
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[TestCase(0xFF800001u, 'N', false, 0xFFC00001u)]
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[TestCase(0xFF800001u, 'P', false, 0xFFC00001u)]
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[TestCase(0xFF800001u, 'M', false, 0xFFC00001u)]
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@ -41,7 +37,6 @@ namespace Ryujinx.Tests.Cpu
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[TestCase(0xFF800001u, 'P', true, 0x7FC00000u)]
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[TestCase(0xFF800001u, 'M', true, 0x7FC00000u)]
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[TestCase(0xFF800001u, 'Z', true, 0x7FC00000u)]
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//QNaN
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[TestCase(0x7FC00002u, 'N', false, 0x7FC00002u)]
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[TestCase(0x7FC00002u, 'P', false, 0x7FC00002u)]
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[TestCase(0x7FC00002u, 'M', false, 0x7FC00002u)]
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