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Update tests

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This commit is contained in:
gdkchan 2019-05-30 20:25:58 -03:00
commit be10223690
2 changed files with 22 additions and 54 deletions
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12
Ryujinx.Tests/Cpu/CpuTest.cs
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@ -70,6 +70,7 @@ namespace Ryujinx.Tests.Cpu
Marshal.FreeHGlobal(_ramPointer); Marshal.FreeHGlobal(_ramPointer);
_memory = null; _memory = null;
_context = null; _context = null;
_translator = null;
_unicornEmu = null; _unicornEmu = null;
} }
@ -171,7 +172,7 @@ namespace Ryujinx.Tests.Cpu
if (_unicornAvailable) if (_unicornAvailable)
{ {
_unicornEmu.RunForCount((ulong)(_currAddress - _entryPoint - 8) / 4); _unicornEmu.RunForCount((ulong)(_currAddress - _entryPoint - 4) / 4);
} }
} }
@ -196,16 +197,7 @@ namespace Ryujinx.Tests.Cpu
int fpcr = 0, int fpcr = 0,
int fpsr = 0) int fpsr = 0)
{ {
/*using (System.IO.FileStream fs = new System.IO.FileStream("D:\\code.bin", System.IO.FileMode.Create))
{
System.IO.BinaryWriter bw = new System.IO.BinaryWriter(fs);
bw.Write(opcode);
bw.Write(0xD65F03C0);
}*/
Opcode(opcode); Opcode(opcode);
Opcode(0xD4200000); // BRK #0
Opcode(0xD65F03C0); // RET Opcode(0xD65F03C0); // RET
SetContext(x0, x1, x2, x3, x31, v0, v1, v2, v3, v4, v5, v30, v31, overflow, carry, zero, negative, fpcr, fpsr); SetContext(x0, x1, x2, x3, x31, v0, v1, v2, v3, v4, v5, v30, v31, overflow, carry, zero, negative, fpcr, fpsr);
ExecuteOpcodes(); ExecuteOpcodes();

52
Ryujinx.Tests/Cpu/CpuTestMisc.cs
View file

@ -33,7 +33,6 @@ namespace Ryujinx.Tests.Cpu
SetContext(x0: xn); SetContext(x0: xn);
Opcode(opCmn); Opcode(opCmn);
Opcode(opCset); Opcode(opCset);
Opcode(0xD4200000); // BRK #0
Opcode(0xD65F03C0); // RET Opcode(0xD65F03C0); // RET
ExecuteOpcodes(); ExecuteOpcodes();
@ -59,7 +58,6 @@ namespace Ryujinx.Tests.Cpu
SetContext(x0: wn); SetContext(x0: wn);
Opcode(opCmn); Opcode(opCmn);
Opcode(opCset); Opcode(opCset);
Opcode(0xD4200000); // BRK #0
Opcode(0xD65F03C0); // RET Opcode(0xD65F03C0); // RET
ExecuteOpcodes(); ExecuteOpcodes();
@ -85,7 +83,6 @@ namespace Ryujinx.Tests.Cpu
SetContext(x0: xn); SetContext(x0: xn);
Opcode(opCmp); Opcode(opCmp);
Opcode(opCset); Opcode(opCset);
Opcode(0xD4200000); // BRK #0
Opcode(0xD65F03C0); // RET Opcode(0xD65F03C0); // RET
ExecuteOpcodes(); ExecuteOpcodes();
@ -111,7 +108,6 @@ namespace Ryujinx.Tests.Cpu
SetContext(x0: wn); SetContext(x0: wn);
Opcode(opCmp); Opcode(opCmp);
Opcode(opCset); Opcode(opCset);
Opcode(0xD4200000); // BRK #0
Opcode(0xD65F03C0); // RET Opcode(0xD65F03C0); // RET
ExecuteOpcodes(); ExecuteOpcodes();
@ -134,7 +130,6 @@ namespace Ryujinx.Tests.Cpu
SUB W0, W0, #3 SUB W0, W0, #3
MUL W0, W1, W0 MUL W0, W1, W0
SDIV W0, W2, W0 SDIV W0, W2, W0
BRK #0
RET RET
*/ */
@ -146,7 +141,6 @@ namespace Ryujinx.Tests.Cpu
Opcode(0x51000C00); Opcode(0x51000C00);
Opcode(0x1B007C20); Opcode(0x1B007C20);
Opcode(0x1AC00C40); Opcode(0x1AC00C40);
Opcode(0xD4200000);
Opcode(0xD65F03C0); Opcode(0xD65F03C0);
ExecuteOpcodes(); ExecuteOpcodes();
@ -183,20 +177,16 @@ namespace Ryujinx.Tests.Cpu
FADD S0, S0, S1 FADD S0, S0, S1
FDIV S0, S2, S0 FDIV S0, S2, S0
FMUL S0, S0, S0 FMUL S0, S0, S0
BRK #0
RET RET
*/ */
SetContext( SetContext(v0: MakeVectorScalar(a), v1: MakeVectorScalar(b));
v0: MakeVectorScalar(a),
v1: MakeVectorScalar(b));
Opcode(0x1E2E1002); Opcode(0x1E2E1002);
Opcode(0x1E201840); Opcode(0x1E201840);
Opcode(0x1E211841); Opcode(0x1E211841);
Opcode(0x1E212800); Opcode(0x1E212800);
Opcode(0x1E201840); Opcode(0x1E201840);
Opcode(0x1E200800); Opcode(0x1E200800);
Opcode(0xD4200000);
Opcode(0xD65F03C0); Opcode(0xD65F03C0);
ExecuteOpcodes(); ExecuteOpcodes();
@ -233,27 +223,23 @@ namespace Ryujinx.Tests.Cpu
FADD D0, D0, D1 FADD D0, D0, D1
FDIV D0, D2, D0 FDIV D0, D2, D0
FMUL D0, D0, D0 FMUL D0, D0, D0
BRK #0
RET RET
*/ */
SetContext( SetContext(v0: MakeVectorScalar(a), v1: MakeVectorScalar(b));
v0: MakeVectorScalar(a),
v1: MakeVectorScalar(b));
Opcode(0x1E6E1002); Opcode(0x1E6E1002);
Opcode(0x1E601840); Opcode(0x1E601840);
Opcode(0x1E611841); Opcode(0x1E611841);
Opcode(0x1E612800); Opcode(0x1E612800);
Opcode(0x1E601840); Opcode(0x1E601840);
Opcode(0x1E600800); Opcode(0x1E600800);
Opcode(0xD4200000);
Opcode(0xD65F03C0); Opcode(0xD65F03C0);
ExecuteOpcodes(); ExecuteOpcodes();
Assert.That(GetContext().GetV(0).AsDouble(), Is.EqualTo(16d)); Assert.That(GetContext().GetV(0).AsDouble(), Is.EqualTo(16d));
} }
[Test] [Test, Ignore("The Tester supports only one return point.")]
public void MiscF([Range(0u, 92u, 1u)] uint a) public void MiscF([Range(0u, 92u, 1u)] uint a)
{ {
ulong Fn(uint n) ulong Fn(uint n)
@ -277,9 +263,9 @@ namespace Ryujinx.Tests.Cpu
/* /*
0x0000000000001000: MOV W4, W0 0x0000000000001000: MOV W4, W0
0x0000000000001004: CBZ W0, #0x3C 0x0000000000001004: CBZ W0, #0x34
0x0000000000001008: CMP W0, #1 0x0000000000001008: CMP W0, #1
0x000000000000100C: B.LS #0x48 0x000000000000100C: B.LS #0x34
0x0000000000001010: MOVZ W2, #0x2 0x0000000000001010: MOVZ W2, #0x2
0x0000000000001014: MOVZ X1, #0x1 0x0000000000001014: MOVZ X1, #0x1
0x0000000000001018: MOVZ X3, #0 0x0000000000001018: MOVZ X3, #0
@ -288,22 +274,19 @@ namespace Ryujinx.Tests.Cpu
0x0000000000001024: MOV X3, X1 0x0000000000001024: MOV X3, X1
0x0000000000001028: MOV X1, X0 0x0000000000001028: MOV X1, X0
0x000000000000102C: CMP W4, W2 0x000000000000102C: CMP W4, W2
0x0000000000001030: B.HS #0x1C 0x0000000000001030: B.HS #-0x14
0x0000000000001034: BRK #0 0x0000000000001034: RET
0x0000000000001038: RET 0x0000000000001038: MOVZ X0, #0
0x000000000000103C: MOVZ X0, #0 0x000000000000103C: RET
0x0000000000001040: BRK #0 0x0000000000001040: MOVZ X0, #0x1
0x0000000000001044: RET 0x0000000000001044: RET
0x0000000000001048: MOVZ X0, #0x1
0x000000000000104C: BRK #0
0x0000000000001050: RET
*/ */
SetContext(x0: a); SetContext(x0: a);
Opcode(0x2A0003E4); Opcode(0x2A0003E4);
Opcode(0x340001C0); Opcode(0x340001A0);
Opcode(0x7100041F); Opcode(0x7100041F);
Opcode(0x540001E9); Opcode(0x540001A9);
Opcode(0x52800042); Opcode(0x52800042);
Opcode(0xD2800021); Opcode(0xD2800021);
Opcode(0xD2800003); Opcode(0xD2800003);
@ -313,13 +296,10 @@ namespace Ryujinx.Tests.Cpu
Opcode(0xAA0003E1); Opcode(0xAA0003E1);
Opcode(0x6B02009F); Opcode(0x6B02009F);
Opcode(0x54FFFF62); Opcode(0x54FFFF62);
Opcode(0xD4200000);
Opcode(0xD65F03C0); Opcode(0xD65F03C0);
Opcode(0xD2800000); Opcode(0xD2800000);
Opcode(0xD4200000);
Opcode(0xD65F03C0); Opcode(0xD65F03C0);
Opcode(0xD2800020); Opcode(0xD2800020);
Opcode(0xD4200000);
Opcode(0xD65F03C0); Opcode(0xD65F03C0);
ExecuteOpcodes(); ExecuteOpcodes();
@ -336,14 +316,12 @@ namespace Ryujinx.Tests.Cpu
0x0000000000001000: MOV X0, #2 0x0000000000001000: MOV X0, #2
0x0000000000001004: MOV X1, #3 0x0000000000001004: MOV X1, #3
0x0000000000001008: ADD X0, X0, X1 0x0000000000001008: ADD X0, X0, X1
0x000000000000100C: BRK #0 0x000000000000100C: RET
0x0000000000001010: RET
*/ */
Opcode(0xD2800040); Opcode(0xD2800040);
Opcode(0xD2800061); Opcode(0xD2800061);
Opcode(0x8B010000); Opcode(0x8B010000);
Opcode(0xD4200000);
Opcode(0xD65F03C0); Opcode(0xD65F03C0);
ExecuteOpcodes(); ExecuteOpcodes();
@ -355,14 +333,12 @@ namespace Ryujinx.Tests.Cpu
0x0000000000001000: MOV X0, #3 0x0000000000001000: MOV X0, #3
0x0000000000001004: MOV X1, #2 0x0000000000001004: MOV X1, #2
0x0000000000001008: ADD X0, X0, X1 0x0000000000001008: ADD X0, X0, X1
0x000000000000100C: BRK #0 0x000000000000100C: RET
0x0000000000001010: RET
*/ */
Opcode(0xD2800060); Opcode(0xD2800060);
Opcode(0xD2800041); Opcode(0xD2800041);
Opcode(0x8B010000); Opcode(0x8B010000);
Opcode(0xD4200000);
Opcode(0xD65F03C0); Opcode(0xD65F03C0);
ExecuteOpcodes(); ExecuteOpcodes();