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Rename OpCode class

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This commit is contained in:
Alex Barney 2018-10-30 16:21:08 -05:00
commit c595bcc9d6
87 changed files with 901 additions and 901 deletions
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6
ChocolArm64/Decoders/Block.cs
View file

@ -10,11 +10,11 @@ namespace ChocolArm64.Decoders
public Block Next { get; set; } public Block Next { get; set; }
public Block Branch { get; set; } public Block Branch { get; set; }
public List<AOpCode> OpCodes { get; private set; } public List<OpCode64> OpCodes { get; private set; }
public Block() public Block()
{ {
OpCodes = new List<AOpCode>(); OpCodes = new List<OpCode64>();
} }
public Block(long position) : this() public Block(long position) : this()
@ -22,7 +22,7 @@ namespace ChocolArm64.Decoders
Position = position; Position = position;
} }
public AOpCode GetLastOp() public OpCode64 GetLastOp()
{ {
if (OpCodes.Count > 0) if (OpCodes.Count > 0)
{ {

26
ChocolArm64/Decoders/Decoder.cs
View file

@ -69,9 +69,9 @@ namespace ChocolArm64.Decoders
{ {
bool hasCachedSub = false; bool hasCachedSub = false;
AOpCode lastOp = current.GetLastOp(); OpCode64 lastOp = current.GetLastOp();
if (lastOp is OpCodeBImm op) if (lastOp is OpCodeBImm64 op)
{ {
if (op.Emitter == InstEmit.Bl) if (op.Emitter == InstEmit.Bl)
{ {
@ -83,8 +83,8 @@ namespace ChocolArm64.Decoders
} }
} }
if (!((lastOp is OpCodeBImmAl) || if (!((lastOp is OpCodeBImmAl64) ||
(lastOp is OpCodeBReg)) || hasCachedSub) (lastOp is OpCodeBReg64)) || hasCachedSub)
{ {
current.Next = Enqueue(current.EndPosition); current.Next = Enqueue(current.EndPosition);
} }
@ -151,7 +151,7 @@ namespace ChocolArm64.Decoders
{ {
long position = block.Position; long position = block.Position;
AOpCode opCode; OpCode64 opCode;
do do
{ {
@ -168,20 +168,20 @@ namespace ChocolArm64.Decoders
block.EndPosition = position; block.EndPosition = position;
} }
private static bool IsBranch(AOpCode opCode) private static bool IsBranch(OpCode64 opCode)
{ {
return opCode is OpCodeBImm || return opCode is OpCodeBImm64 ||
opCode is OpCodeBReg; opCode is OpCodeBReg64;
} }
private static bool IsException(AOpCode opCode) private static bool IsException(OpCode64 opCode)
{ {
return opCode.Emitter == InstEmit.Brk || return opCode.Emitter == InstEmit.Brk ||
opCode.Emitter == InstEmit.Svc || opCode.Emitter == InstEmit.Svc ||
opCode.Emitter == InstEmit.Und; opCode.Emitter == InstEmit.Und;
} }
public static AOpCode DecodeOpCode(CpuThreadState state, MemoryManager memory, long position) public static OpCode64 DecodeOpCode(CpuThreadState state, MemoryManager memory, long position)
{ {
int opCode = memory.ReadInt32(position); int opCode = memory.ReadInt32(position);
@ -197,7 +197,7 @@ namespace ChocolArm64.Decoders
inst = OpCodeTable.GetInstA32(opCode); inst = OpCodeTable.GetInstA32(opCode);
} }
AOpCode decodedOpCode = new AOpCode(Inst.Undefined, position, opCode); OpCode64 decodedOpCode = new OpCode64(Inst.Undefined, position, opCode);
if (inst.Type != null) if (inst.Type != null)
{ {
@ -207,7 +207,7 @@ namespace ChocolArm64.Decoders
return decodedOpCode; return decodedOpCode;
} }
private static AOpCode MakeOpCode(Type type, Inst inst, long position, int opCode) private static OpCode64 MakeOpCode(Type type, Inst inst, long position, int opCode)
{ {
if (type == null) if (type == null)
{ {
@ -216,7 +216,7 @@ namespace ChocolArm64.Decoders
OpActivator createInstance = _opActivators.GetOrAdd(type, CacheOpActivator); OpActivator createInstance = _opActivators.GetOrAdd(type, CacheOpActivator);
return (AOpCode)createInstance(inst, position, opCode); return (OpCode64)createInstance(inst, position, opCode);
} }
private static OpActivator CacheOpActivator(Type type) private static OpActivator CacheOpActivator(Type type)

2
ChocolArm64/Decoders/IOpCode.cs → ChocolArm64/Decoders/IOpCode64.cs
View file

@ -3,7 +3,7 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
interface IOpCode interface IOpCode64
{ {
long Position { get; } long Position { get; }

2
ChocolArm64/Decoders/IOpCodeAlu.cs → ChocolArm64/Decoders/IOpCodeAlu64.cs
View file

@ -1,6 +1,6 @@
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
interface IOpCodeAlu : IOpCode interface IOpCodeAlu64 : IOpCode64
{ {
int Rd { get; } int Rd { get; }
int Rn { get; } int Rn { get; }

2
ChocolArm64/Decoders/IOpCodeAluImm.cs → ChocolArm64/Decoders/IOpCodeAluImm64.cs
View file

@ -1,6 +1,6 @@
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
interface IOpCodeAluImm : IOpCodeAlu interface IOpCodeAluImm64 : IOpCodeAlu64
{ {
long Imm { get; } long Imm { get; }
} }

2
ChocolArm64/Decoders/IOpCodeAluRs.cs → ChocolArm64/Decoders/IOpCodeAluRs64.cs
View file

@ -1,6 +1,6 @@
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
interface IOpCodeAluRs : IOpCodeAlu interface IOpCodeAluRs64 : IOpCodeAlu64
{ {
int Shift { get; } int Shift { get; }
int Rm { get; } int Rm { get; }

2
ChocolArm64/Decoders/IOpCodeAluRx.cs → ChocolArm64/Decoders/IOpCodeAluRx64.cs
View file

@ -1,6 +1,6 @@
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
interface IOpCodeAluRx : IOpCodeAlu interface IOpCodeAluRx64 : IOpCodeAlu64
{ {
int Shift { get; } int Shift { get; }
int Rm { get; } int Rm { get; }

2
ChocolArm64/Decoders/IOpCodeCond.cs → ChocolArm64/Decoders/IOpCodeCond64.cs
View file

@ -1,6 +1,6 @@
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
interface IOpCodeCond : IOpCode interface IOpCodeCond64 : IOpCode64
{ {
Cond Cond { get; } Cond Cond { get; }
} }

2
ChocolArm64/Decoders/IOpCodeLit.cs → ChocolArm64/Decoders/IOpCodeLit64.cs
View file

@ -1,6 +1,6 @@
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
interface IOpCodeLit : IOpCode interface IOpCodeLit64 : IOpCode64
{ {
int Rt { get; } int Rt { get; }
long Imm { get; } long Imm { get; }

2
ChocolArm64/Decoders/IOpCodeSimd.cs → ChocolArm64/Decoders/IOpCodeSimd64.cs
View file

@ -1,6 +1,6 @@
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
interface IOpCodeSimd : IOpCode interface IOpCodeSimd64 : IOpCode64
{ {
int Size { get; } int Size { get; }
} }

4
ChocolArm64/Decoders/AOpCode.cs → ChocolArm64/Decoders/OpCode64.cs
View file

@ -4,7 +4,7 @@ using System;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class AOpCode : IOpCode class OpCode64 : IOpCode64
{ {
public long Position { get; private set; } public long Position { get; private set; }
public int RawOpCode { get; private set; } public int RawOpCode { get; private set; }
@ -13,7 +13,7 @@ namespace ChocolArm64.Decoders
public InstInterpreter Interpreter { get; protected set; } public InstInterpreter Interpreter { get; protected set; }
public RegisterSize RegisterSize { get; protected set; } public RegisterSize RegisterSize { get; protected set; }
public AOpCode(Inst inst, long position, int opCode) public OpCode64(Inst inst, long position, int opCode)
{ {
Position = position; Position = position;
RawOpCode = opCode; RawOpCode = opCode;

4
ChocolArm64/Decoders/OpCodeAluImm.cs → ChocolArm64/Decoders/OpCode64AluImm.cs
View file

@ -3,11 +3,11 @@ using System;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeAluImm : OpCodeAlu, IOpCodeAluImm class OpCode64AluImm : OpCodeAlu64, IOpCodeAluImm64
{ {
public long Imm { get; private set; } public long Imm { get; private set; }
public OpCodeAluImm(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCode64AluImm(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
if (DataOp == DataOp.Arithmetic) if (DataOp == DataOp.Arithmetic)
{ {

4
ChocolArm64/Decoders/OpCodeMemLit.cs → ChocolArm64/Decoders/OpCode64MemLit64.cs
View file

@ -2,7 +2,7 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeMemLit : AOpCode, IOpCodeLit class OpCode64MemLit64 : OpCode64, IOpCodeLit64
{ {
public int Rt { get; private set; } public int Rt { get; private set; }
public long Imm { get; private set; } public long Imm { get; private set; }
@ -10,7 +10,7 @@ namespace ChocolArm64.Decoders
public bool Signed { get; private set; } public bool Signed { get; private set; }
public bool Prefetch { get; private set; } public bool Prefetch { get; private set; }
public OpCodeMemLit(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCode64MemLit64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rt = opCode & 0x1f; Rt = opCode & 0x1f;

4
ChocolArm64/Decoders/OpCodeAdr.cs → ChocolArm64/Decoders/OpCodeAdr64.cs
View file

@ -2,12 +2,12 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeAdr : AOpCode class OpCodeAdr64 : OpCode64
{ {
public int Rd { get; private set; } public int Rd { get; private set; }
public long Imm { get; private set; } public long Imm { get; private set; }
public OpCodeAdr(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeAdr64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rd = opCode & 0x1f; Rd = opCode & 0x1f;

4
ChocolArm64/Decoders/OpCodeAlu.cs → ChocolArm64/Decoders/OpCodeAlu64.cs
View file

@ -3,14 +3,14 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeAlu : AOpCode, IOpCodeAlu class OpCodeAlu64 : OpCode64, IOpCodeAlu64
{ {
public int Rd { get; protected set; } public int Rd { get; protected set; }
public int Rn { get; private set; } public int Rn { get; private set; }
public DataOp DataOp { get; private set; } public DataOp DataOp { get; private set; }
public OpCodeAlu(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeAlu64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rd = (opCode >> 0) & 0x1f; Rd = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f; Rn = (opCode >> 5) & 0x1f;

4
ChocolArm64/Decoders/OpCodeAluRs.cs → ChocolArm64/Decoders/OpCodeAluRs64.cs
View file

@ -2,14 +2,14 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeAluRs : OpCodeAlu, IOpCodeAluRs class OpCodeAluRs64 : OpCodeAlu64, IOpCodeAluRs64
{ {
public int Shift { get; private set; } public int Shift { get; private set; }
public int Rm { get; private set; } public int Rm { get; private set; }
public ShiftType ShiftType { get; private set; } public ShiftType ShiftType { get; private set; }
public OpCodeAluRs(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeAluRs64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
int shift = (opCode >> 10) & 0x3f; int shift = (opCode >> 10) & 0x3f;

4
ChocolArm64/Decoders/OpCodeAluRx.cs → ChocolArm64/Decoders/OpCodeAluRx64.cs
View file

@ -2,14 +2,14 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeAluRx : OpCodeAlu, IOpCodeAluRx class OpCodeAluRx64 : OpCodeAlu64, IOpCodeAluRx64
{ {
public int Shift { get; private set; } public int Shift { get; private set; }
public int Rm { get; private set; } public int Rm { get; private set; }
public IntType IntType { get; private set; } public IntType IntType { get; private set; }
public OpCodeAluRx(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeAluRx64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Shift = (opCode >> 10) & 0x7; Shift = (opCode >> 10) & 0x7;
IntType = (IntType)((opCode >> 13) & 0x7); IntType = (IntType)((opCode >> 13) & 0x7);

11
ChocolArm64/Decoders/OpCodeBImm.cs
View file

@ -1,11 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeBImm : AOpCode
{
public long Imm { get; protected set; }
public OpCodeBImm(Inst inst, long position, int opCode) : base(inst, position, opCode) { }
}
}

11
ChocolArm64/Decoders/OpCodeBImm64.cs Normal file
View file

@ -0,0 +1,11 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeBImm64 : OpCode64
{
public long Imm { get; protected set; }
public OpCodeBImm64(Inst inst, long position, int opCode) : base(inst, position, opCode) { }
}
}

4
ChocolArm64/Decoders/OpCodeBImmAl.cs → ChocolArm64/Decoders/OpCodeBImmAl64.cs
View file

@ -2,9 +2,9 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeBImmAl : OpCodeBImm class OpCodeBImmAl64 : OpCodeBImm64
{ {
public OpCodeBImmAl(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeBImmAl64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Imm = position + DecoderHelper.DecodeImm26_2(opCode); Imm = position + DecoderHelper.DecodeImm26_2(opCode);
} }

4
ChocolArm64/Decoders/OpCodeBImmCmp.cs → ChocolArm64/Decoders/OpCodeBImmCmp64.cs
View file

@ -3,11 +3,11 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeBImmCmp : OpCodeBImm class OpCodeBImmCmp64 : OpCodeBImm64
{ {
public int Rt { get; private set; } public int Rt { get; private set; }
public OpCodeBImmCmp(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeBImmCmp64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rt = opCode & 0x1f; Rt = opCode & 0x1f;

4
ChocolArm64/Decoders/OpCodeBImmCond.cs → ChocolArm64/Decoders/OpCodeBImmCond64.cs
View file

@ -2,11 +2,11 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeBImmCond : OpCodeBImm, IOpCodeCond class OpCodeBImmCond64 : OpCodeBImm64, IOpCodeCond64
{ {
public Cond Cond { get; private set; } public Cond Cond { get; private set; }
public OpCodeBImmCond(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeBImmCond64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
int o0 = (opCode >> 4) & 1; int o0 = (opCode >> 4) & 1;

4
ChocolArm64/Decoders/OpCodeBImmTest.cs → ChocolArm64/Decoders/OpCodeBImmTest64.cs
View file

@ -2,12 +2,12 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeBImmTest : OpCodeBImm class OpCodeBImmTest64 : OpCodeBImm64
{ {
public int Rt { get; private set; } public int Rt { get; private set; }
public int Pos { get; private set; } public int Pos { get; private set; }
public OpCodeBImmTest(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeBImmTest64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rt = opCode & 0x1f; Rt = opCode & 0x1f;

4
ChocolArm64/Decoders/OpCodeBReg.cs → ChocolArm64/Decoders/OpCodeBReg64.cs
View file

@ -2,11 +2,11 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeBReg : AOpCode class OpCodeBReg64 : OpCode64
{ {
public int Rn { get; private set; } public int Rn { get; private set; }
public OpCodeBReg(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeBReg64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
int op4 = (opCode >> 0) & 0x1f; int op4 = (opCode >> 0) & 0x1f;
int op2 = (opCode >> 16) & 0x1f; int op2 = (opCode >> 16) & 0x1f;

4
ChocolArm64/Decoders/OpCodeBfm.cs → ChocolArm64/Decoders/OpCodeBfm64.cs
View file

@ -2,14 +2,14 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeBfm : OpCodeAlu class OpCodeBfm64 : OpCodeAlu64
{ {
public long WMask { get; private set; } public long WMask { get; private set; }
public long TMask { get; private set; } public long TMask { get; private set; }
public int Pos { get; private set; } public int Pos { get; private set; }
public int Shift { get; private set; } public int Shift { get; private set; }
public OpCodeBfm(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeBfm64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
var bm = DecoderHelper.DecodeBitMask(opCode, false); var bm = DecoderHelper.DecodeBitMask(opCode, false);

4
ChocolArm64/Decoders/OpCodeCcmp.cs → ChocolArm64/Decoders/OpCodeCcmp64.cs
View file

@ -3,14 +3,14 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeCcmp : OpCodeAlu, IOpCodeCond class OpCodeCcmp64 : OpCodeAlu64, IOpCodeCond64
{ {
public int Nzcv { get; private set; } public int Nzcv { get; private set; }
protected int RmImm; protected int RmImm;
public Cond Cond { get; private set; } public Cond Cond { get; private set; }
public OpCodeCcmp(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeCcmp64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
int o3 = (opCode >> 4) & 1; int o3 = (opCode >> 4) & 1;

11
ChocolArm64/Decoders/OpCodeCcmpImm.cs
View file

@ -1,11 +0,0 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeCcmpImm : OpCodeCcmp, IOpCodeAluImm
{
public long Imm => RmImm;
public OpCodeCcmpImm(Inst inst, long position, int opCode) : base(inst, position, opCode) { }
}
}

11
ChocolArm64/Decoders/OpCodeCcmpImm64.cs Normal file
View file

@ -0,0 +1,11 @@
using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders
{
class OpCodeCcmpImm64 : OpCodeCcmp64, IOpCodeAluImm64
{
public long Imm => RmImm;
public OpCodeCcmpImm64(Inst inst, long position, int opCode) : base(inst, position, opCode) { }
}
}

4
ChocolArm64/Decoders/OpCodeCcmpReg.cs → ChocolArm64/Decoders/OpCodeCcmpReg64.cs
View file

@ -2,7 +2,7 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeCcmpReg : OpCodeCcmp, IOpCodeAluRs class OpCodeCcmpReg64 : OpCodeCcmp64, IOpCodeAluRs64
{ {
public int Rm => RmImm; public int Rm => RmImm;
@ -10,6 +10,6 @@ namespace ChocolArm64.Decoders
public ShiftType ShiftType => ShiftType.Lsl; public ShiftType ShiftType => ShiftType.Lsl;
public OpCodeCcmpReg(Inst inst, long position, int opCode) : base(inst, position, opCode) { } public OpCodeCcmpReg64(Inst inst, long position, int opCode) : base(inst, position, opCode) { }
} }
} }

4
ChocolArm64/Decoders/OpCodeCsel.cs → ChocolArm64/Decoders/OpCodeCsel64.cs
View file

@ -2,13 +2,13 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeCsel : OpCodeAlu, IOpCodeCond class OpCodeCsel64 : OpCodeAlu64, IOpCodeCond64
{ {
public int Rm { get; private set; } public int Rm { get; private set; }
public Cond Cond { get; private set; } public Cond Cond { get; private set; }
public OpCodeCsel(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeCsel64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rm = (opCode >> 16) & 0x1f; Rm = (opCode >> 16) & 0x1f;
Cond = (Cond)((opCode >> 12) & 0xf); Cond = (Cond)((opCode >> 12) & 0xf);

4
ChocolArm64/Decoders/OpCodeException.cs → ChocolArm64/Decoders/OpCodeException64.cs
View file

@ -2,11 +2,11 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeException : AOpCode class OpCodeException64 : OpCode64
{ {
public int Id { get; private set; } public int Id { get; private set; }
public OpCodeException(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeException64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Id = (opCode >> 5) & 0xffff; Id = (opCode >> 5) & 0xffff;
} }

4
ChocolArm64/Decoders/OpCodeMem.cs → ChocolArm64/Decoders/OpCodeMem64.cs
View file

@ -2,14 +2,14 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeMem : AOpCode class OpCodeMem64 : OpCode64
{ {
public int Rt { get; protected set; } public int Rt { get; protected set; }
public int Rn { get; protected set; } public int Rn { get; protected set; }
public int Size { get; protected set; } public int Size { get; protected set; }
public bool Extend64 { get; protected set; } public bool Extend64 { get; protected set; }
public OpCodeMem(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeMem64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rt = (opCode >> 0) & 0x1f; Rt = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f; Rn = (opCode >> 5) & 0x1f;

4
ChocolArm64/Decoders/OpCodeMemEx.cs → ChocolArm64/Decoders/OpCodeMemEx64.cs
View file

@ -2,12 +2,12 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeMemEx : OpCodeMem class OpCodeMemEx64 : OpCodeMem64
{ {
public int Rt2 { get; private set; } public int Rt2 { get; private set; }
public int Rs { get; private set; } public int Rs { get; private set; }
public OpCodeMemEx(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeMemEx64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rt2 = (opCode >> 10) & 0x1f; Rt2 = (opCode >> 10) & 0x1f;
Rs = (opCode >> 16) & 0x1f; Rs = (opCode >> 16) & 0x1f;

4
ChocolArm64/Decoders/OpCodeMemImm.cs → ChocolArm64/Decoders/OpCodeMemImm64.cs
View file

@ -2,7 +2,7 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeMemImm : OpCodeMem class OpCodeMemImm64 : OpCodeMem64
{ {
public long Imm { get; protected set; } public long Imm { get; protected set; }
public bool WBack { get; protected set; } public bool WBack { get; protected set; }
@ -18,7 +18,7 @@ namespace ChocolArm64.Decoders
Unsigned Unsigned
} }
public OpCodeMemImm(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeMemImm64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Extend64 = ((opCode >> 22) & 3) == 2; Extend64 = ((opCode >> 22) & 3) == 2;
WBack = ((opCode >> 24) & 1) == 0; WBack = ((opCode >> 24) & 1) == 0;

4
ChocolArm64/Decoders/OpCodeMemPair.cs → ChocolArm64/Decoders/OpCodeMemPair64.cs
View file

@ -2,11 +2,11 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeMemPair : OpCodeMemImm class OpCodeMemPair64 : OpCodeMemImm64
{ {
public int Rt2 { get; private set; } public int Rt2 { get; private set; }
public OpCodeMemPair(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeMemPair64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rt2 = (opCode >> 10) & 0x1f; Rt2 = (opCode >> 10) & 0x1f;
WBack = ((opCode >> 23) & 0x1) != 0; WBack = ((opCode >> 23) & 0x1) != 0;

4
ChocolArm64/Decoders/OpCodeMemReg.cs → ChocolArm64/Decoders/OpCodeMemReg64.cs
View file

@ -2,14 +2,14 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeMemReg : OpCodeMem class OpCodeMemReg64 : OpCodeMem64
{ {
public bool Shift { get; private set; } public bool Shift { get; private set; }
public int Rm { get; private set; } public int Rm { get; private set; }
public IntType IntType { get; private set; } public IntType IntType { get; private set; }
public OpCodeMemReg(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeMemReg64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Shift = ((opCode >> 12) & 0x1) != 0; Shift = ((opCode >> 12) & 0x1) != 0;
IntType = (IntType)((opCode >> 13) & 0x7); IntType = (IntType)((opCode >> 13) & 0x7);

4
ChocolArm64/Decoders/OpCodeMov.cs → ChocolArm64/Decoders/OpCodeMov64.cs
View file

@ -3,13 +3,13 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeMov : AOpCode class OpCodeMov64 : OpCode64
{ {
public int Rd { get; private set; } public int Rd { get; private set; }
public long Imm { get; private set; } public long Imm { get; private set; }
public int Pos { get; private set; } public int Pos { get; private set; }
public OpCodeMov(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeMov64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
int p1 = (opCode >> 22) & 1; int p1 = (opCode >> 22) & 1;
int sf = (opCode >> 31) & 1; int sf = (opCode >> 31) & 1;

4
ChocolArm64/Decoders/OpCodeMul.cs → ChocolArm64/Decoders/OpCodeMul64.cs
View file

@ -2,12 +2,12 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeMul : OpCodeAlu class OpCodeMul64 : OpCodeAlu64
{ {
public int Rm { get; private set; } public int Rm { get; private set; }
public int Ra { get; private set; } public int Ra { get; private set; }
public OpCodeMul(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeMul64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Ra = (opCode >> 10) & 0x1f; Ra = (opCode >> 10) & 0x1f;
Rm = (opCode >> 16) & 0x1f; Rm = (opCode >> 16) & 0x1f;

4
ChocolArm64/Decoders/OpCodeSimd.cs → ChocolArm64/Decoders/OpCodeSimd64.cs
View file

@ -3,14 +3,14 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimd : AOpCode, IOpCodeSimd class OpCodeSimd64 : OpCode64, IOpCodeSimd64
{ {
public int Rd { get; private set; } public int Rd { get; private set; }
public int Rn { get; private set; } public int Rn { get; private set; }
public int Opc { get; private set; } public int Opc { get; private set; }
public int Size { get; protected set; } public int Size { get; protected set; }
public OpCodeSimd(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimd64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rd = (opCode >> 0) & 0x1f; Rd = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f; Rn = (opCode >> 5) & 0x1f;

4
ChocolArm64/Decoders/OpCodeSimdCvt.cs → ChocolArm64/Decoders/OpCodeSimdCvt64.cs
View file

@ -3,11 +3,11 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimdCvt : OpCodeSimd class OpCodeSimdCvt64 : OpCodeSimd64
{ {
public int FBits { get; private set; } public int FBits { get; private set; }
public OpCodeSimdCvt(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdCvt64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
//TODO: //TODO:
//Und of Fixed Point variants. //Und of Fixed Point variants.

4
ChocolArm64/Decoders/OpCodeSimdExt.cs → ChocolArm64/Decoders/OpCodeSimdExt64.cs
View file

@ -2,11 +2,11 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimdExt : OpCodeSimdReg class OpCodeSimdExt64 : OpCodeSimdReg64
{ {
public int Imm4 { get; private set; } public int Imm4 { get; private set; }
public OpCodeSimdExt(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdExt64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Imm4 = (opCode >> 11) & 0xf; Imm4 = (opCode >> 11) & 0xf;
} }

4
ChocolArm64/Decoders/OpCodeSimdFcond.cs → ChocolArm64/Decoders/OpCodeSimdFcond64.cs
View file

@ -2,13 +2,13 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimdFcond : OpCodeSimdReg, IOpCodeCond class OpCodeSimdFcond64 : OpCodeSimdReg64, IOpCodeCond64
{ {
public int Nzcv { get; private set; } public int Nzcv { get; private set; }
public Cond Cond { get; private set; } public Cond Cond { get; private set; }
public OpCodeSimdFcond(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdFcond64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Nzcv = (opCode >> 0) & 0xf; Nzcv = (opCode >> 0) & 0xf;
Cond = (Cond)((opCode >> 12) & 0xf); Cond = (Cond)((opCode >> 12) & 0xf);

4
ChocolArm64/Decoders/OpCodeSimdFmov.cs → ChocolArm64/Decoders/OpCodeSimdFmov64.cs
View file

@ -2,13 +2,13 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimdFmov : AOpCode, IOpCodeSimd class OpCodeSimdFmov64 : OpCode64, IOpCodeSimd64
{ {
public int Rd { get; private set; } public int Rd { get; private set; }
public long Imm { get; private set; } public long Imm { get; private set; }
public int Size { get; private set; } public int Size { get; private set; }
public OpCodeSimdFmov(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdFmov64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
int imm5 = (opCode >> 5) & 0x1f; int imm5 = (opCode >> 5) & 0x1f;
int type = (opCode >> 22) & 0x3; int type = (opCode >> 22) & 0x3;

4
ChocolArm64/Decoders/OpCodeSimdImm.cs → ChocolArm64/Decoders/OpCodeSimdImm64.cs
View file

@ -3,13 +3,13 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimdImm : AOpCode, IOpCodeSimd class OpCodeSimdImm64 : OpCode64, IOpCodeSimd64
{ {
public int Rd { get; private set; } public int Rd { get; private set; }
public long Imm { get; private set; } public long Imm { get; private set; }
public int Size { get; private set; } public int Size { get; private set; }
public OpCodeSimdImm(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdImm64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rd = opCode & 0x1f; Rd = opCode & 0x1f;

4
ChocolArm64/Decoders/OpCodeSimdIns.cs → ChocolArm64/Decoders/OpCodeSimdIns64.cs
View file

@ -2,12 +2,12 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimdIns : OpCodeSimd class OpCodeSimdIns64 : OpCodeSimd64
{ {
public int SrcIndex { get; private set; } public int SrcIndex { get; private set; }
public int DstIndex { get; private set; } public int DstIndex { get; private set; }
public OpCodeSimdIns(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdIns64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
int imm4 = (opCode >> 11) & 0xf; int imm4 = (opCode >> 11) & 0xf;
int imm5 = (opCode >> 16) & 0x1f; int imm5 = (opCode >> 16) & 0x1f;

4
ChocolArm64/Decoders/OpCodeSimdMemImm.cs → ChocolArm64/Decoders/OpCodeSimdMemImm64.cs
View file

@ -2,9 +2,9 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimdMemImm : OpCodeMemImm, IOpCodeSimd class OpCodeSimdMemImm64 : OpCodeMemImm64, IOpCodeSimd64
{ {
public OpCodeSimdMemImm(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdMemImm64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Size |= (opCode >> 21) & 4; Size |= (opCode >> 21) & 4;

4
ChocolArm64/Decoders/OpCodeSimdMemLit.cs → ChocolArm64/Decoders/OpCodeSimdMemLit64.cs
View file

@ -2,7 +2,7 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimdMemLit : AOpCode, IOpCodeSimd, IOpCodeLit class OpCodeSimdMemLit64 : OpCode64, IOpCodeSimd64, IOpCodeLit64
{ {
public int Rt { get; private set; } public int Rt { get; private set; }
public long Imm { get; private set; } public long Imm { get; private set; }
@ -10,7 +10,7 @@ namespace ChocolArm64.Decoders
public bool Signed => false; public bool Signed => false;
public bool Prefetch => false; public bool Prefetch => false;
public OpCodeSimdMemLit(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdMemLit64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
int opc = (opCode >> 30) & 3; int opc = (opCode >> 30) & 3;

4
ChocolArm64/Decoders/OpCodeSimdMemMs.cs → ChocolArm64/Decoders/OpCodeSimdMemMs64.cs
View file

@ -3,14 +3,14 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimdMemMs : OpCodeMemReg, IOpCodeSimd class OpCodeSimdMemMs64 : OpCodeMemReg64, IOpCodeSimd64
{ {
public int Reps { get; private set; } public int Reps { get; private set; }
public int SElems { get; private set; } public int SElems { get; private set; }
public int Elems { get; private set; } public int Elems { get; private set; }
public bool WBack { get; private set; } public bool WBack { get; private set; }
public OpCodeSimdMemMs(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdMemMs64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
switch ((opCode >> 12) & 0xf) switch ((opCode >> 12) & 0xf)
{ {

4
ChocolArm64/Decoders/OpCodeSimdMemPair.cs → ChocolArm64/Decoders/OpCodeSimdMemPair64.cs
View file

@ -2,9 +2,9 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimdMemPair : OpCodeMemPair, IOpCodeSimd class OpCodeSimdMemPair64 : OpCodeMemPair64, IOpCodeSimd64
{ {
public OpCodeSimdMemPair(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdMemPair64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Size = ((opCode >> 30) & 3) + 2; Size = ((opCode >> 30) & 3) + 2;

4
ChocolArm64/Decoders/OpCodeSimdMemReg.cs → ChocolArm64/Decoders/OpCodeSimdMemReg64.cs
View file

@ -2,9 +2,9 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimdMemReg : OpCodeMemReg, IOpCodeSimd class OpCodeSimdMemReg64 : OpCodeMemReg64, IOpCodeSimd64
{ {
public OpCodeSimdMemReg(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdMemReg64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Size |= (opCode >> 21) & 4; Size |= (opCode >> 21) & 4;

4
ChocolArm64/Decoders/OpCodeSimdMemSs.cs → ChocolArm64/Decoders/OpCodeSimdMemSs64.cs
View file

@ -3,14 +3,14 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimdMemSs : OpCodeMemReg, IOpCodeSimd class OpCodeSimdMemSs64 : OpCodeMemReg64, IOpCodeSimd64
{ {
public int SElems { get; private set; } public int SElems { get; private set; }
public int Index { get; private set; } public int Index { get; private set; }
public bool Replicate { get; private set; } public bool Replicate { get; private set; }
public bool WBack { get; private set; } public bool WBack { get; private set; }
public OpCodeSimdMemSs(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdMemSs64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
int size = (opCode >> 10) & 3; int size = (opCode >> 10) & 3;
int s = (opCode >> 12) & 1; int s = (opCode >> 12) & 1;

4
ChocolArm64/Decoders/OpCodeSimdReg.cs → ChocolArm64/Decoders/OpCodeSimdReg64.cs
View file

@ -2,13 +2,13 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimdReg : OpCodeSimd class OpCodeSimdReg64 : OpCodeSimd64
{ {
public bool Bit3 { get; private set; } public bool Bit3 { get; private set; }
public int Ra { get; private set; } public int Ra { get; private set; }
public int Rm { get; protected set; } public int Rm { get; protected set; }
public OpCodeSimdReg(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdReg64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Bit3 = ((opCode >> 3) & 0x1) != 0; Bit3 = ((opCode >> 3) & 0x1) != 0;
Ra = (opCode >> 10) & 0x1f; Ra = (opCode >> 10) & 0x1f;

4
ChocolArm64/Decoders/OpCodeSimdRegElem.cs → ChocolArm64/Decoders/OpCodeSimdRegElem64.cs
View file

@ -2,11 +2,11 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimdRegElem : OpCodeSimdReg class OpCodeSimdRegElem64 : OpCodeSimdReg64
{ {
public int Index { get; private set; } public int Index { get; private set; }
public OpCodeSimdRegElem(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdRegElem64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
switch (Size) switch (Size)
{ {

4
ChocolArm64/Decoders/OpCodeSimdRegElemF.cs → ChocolArm64/Decoders/OpCodeSimdRegElemF64.cs
View file

@ -2,11 +2,11 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimdRegElemF : OpCodeSimdReg class OpCodeSimdRegElemF64 : OpCodeSimdReg64
{ {
public int Index { get; private set; } public int Index { get; private set; }
public OpCodeSimdRegElemF(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdRegElemF64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
switch ((opCode >> 21) & 3) // sz:L switch ((opCode >> 21) & 3) // sz:L
{ {

4
ChocolArm64/Decoders/OpCodeSimdShImm.cs → ChocolArm64/Decoders/OpCodeSimdShImm64.cs
View file

@ -2,11 +2,11 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimdShImm : OpCodeSimd class OpCodeSimdShImm64 : OpCodeSimd64
{ {
public int Imm { get; private set; } public int Imm { get; private set; }
public OpCodeSimdShImm(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdShImm64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Imm = (opCode >> 16) & 0x7f; Imm = (opCode >> 16) & 0x7f;

4
ChocolArm64/Decoders/OpCodeSimdTbl.cs → ChocolArm64/Decoders/OpCodeSimdTbl64.cs
View file

@ -2,9 +2,9 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSimdTbl : OpCodeSimdReg class OpCodeSimdTbl64 : OpCodeSimdReg64
{ {
public OpCodeSimdTbl(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdTbl64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Size = ((opCode >> 13) & 3) + 1; Size = ((opCode >> 13) & 3) + 1;
} }

4
ChocolArm64/Decoders/OpCodeSystem.cs → ChocolArm64/Decoders/OpCodeSystem64.cs
View file

@ -2,7 +2,7 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
class OpCodeSystem : AOpCode class OpCodeSystem64 : OpCode64
{ {
public int Rt { get; private set; } public int Rt { get; private set; }
public int Op2 { get; private set; } public int Op2 { get; private set; }
@ -11,7 +11,7 @@ namespace ChocolArm64.Decoders
public int Op1 { get; private set; } public int Op1 { get; private set; }
public int Op0 { get; private set; } public int Op0 { get; private set; }
public OpCodeSystem(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSystem64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rt = (opCode >> 0) & 0x1f; Rt = (opCode >> 0) & 0x1f;
Op2 = (opCode >> 5) & 0x7; Op2 = (opCode >> 5) & 0x7;

2
ChocolArm64/Decoders32/A32OpCode.cs
View file

@ -3,7 +3,7 @@ using ChocolArm64.Instructions;
namespace ChocolArm64.Decoders32 namespace ChocolArm64.Decoders32
{ {
class A32OpCode : AOpCode class A32OpCode : OpCode64
{ {
public Cond Cond { get; private set; } public Cond Cond { get; private set; }

10
ChocolArm64/Instructions/InstEmitAlu.cs
View file

@ -101,7 +101,7 @@ namespace ChocolArm64.Instructions
public static void Cls(ILEmitterCtx context) public static void Cls(ILEmitterCtx context)
{ {
OpCodeAlu op = (OpCodeAlu)context.CurrOp; OpCodeAlu64 op = (OpCodeAlu64)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
@ -114,7 +114,7 @@ namespace ChocolArm64.Instructions
public static void Clz(ILEmitterCtx context) public static void Clz(ILEmitterCtx context)
{ {
OpCodeAlu op = (OpCodeAlu)context.CurrOp; OpCodeAlu64 op = (OpCodeAlu64)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
@ -149,7 +149,7 @@ namespace ChocolArm64.Instructions
public static void Extr(ILEmitterCtx context) public static void Extr(ILEmitterCtx context)
{ {
//TODO: Ensure that the Shift is valid for the Is64Bits. //TODO: Ensure that the Shift is valid for the Is64Bits.
OpCodeAluRs op = (OpCodeAluRs)context.CurrOp; OpCodeAluRs64 op = (OpCodeAluRs64)context.CurrOp;
context.EmitLdintzr(op.Rm); context.EmitLdintzr(op.Rm);
@ -254,7 +254,7 @@ namespace ChocolArm64.Instructions
private static void EmitFallback32_64(ILEmitterCtx context, string name32, string name64) private static void EmitFallback32_64(ILEmitterCtx context, string name32, string name64)
{ {
OpCodeAlu op = (OpCodeAlu)context.CurrOp; OpCodeAlu64 op = (OpCodeAlu64)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
@ -272,7 +272,7 @@ namespace ChocolArm64.Instructions
public static void Rev64(ILEmitterCtx context) public static void Rev64(ILEmitterCtx context)
{ {
OpCodeAlu op = (OpCodeAlu)context.CurrOp; OpCodeAlu64 op = (OpCodeAlu64)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);

16
ChocolArm64/Instructions/InstEmitAluHelper.cs
View file

@ -122,7 +122,7 @@ namespace ChocolArm64.Instructions
public static void EmitDataLoadRm(ILEmitterCtx context) public static void EmitDataLoadRm(ILEmitterCtx context)
{ {
context.EmitLdintzr(((IOpCodeAluRs)context.CurrOp).Rm); context.EmitLdintzr(((IOpCodeAluRs64)context.CurrOp).Rm);
} }
public static void EmitDataLoadOpers(ILEmitterCtx context) public static void EmitDataLoadOpers(ILEmitterCtx context)
@ -133,9 +133,9 @@ namespace ChocolArm64.Instructions
public static void EmitDataLoadRn(ILEmitterCtx context) public static void EmitDataLoadRn(ILEmitterCtx context)
{ {
IOpCodeAlu op = (IOpCodeAlu)context.CurrOp; IOpCodeAlu64 op = (IOpCodeAlu64)context.CurrOp;
if (op.DataOp == DataOp.Logical || op is IOpCodeAluRs) if (op.DataOp == DataOp.Logical || op is IOpCodeAluRs64)
{ {
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
} }
@ -149,11 +149,11 @@ namespace ChocolArm64.Instructions
{ {
switch (context.CurrOp) switch (context.CurrOp)
{ {
case IOpCodeAluImm op: case IOpCodeAluImm64 op:
context.EmitLdc_I(op.Imm); context.EmitLdc_I(op.Imm);
break; break;
case IOpCodeAluRs op: case IOpCodeAluRs64 op:
context.EmitLdintzr(op.Rm); context.EmitLdintzr(op.Rm);
switch (op.ShiftType) switch (op.ShiftType)
@ -165,7 +165,7 @@ namespace ChocolArm64.Instructions
} }
break; break;
case IOpCodeAluRx op: case IOpCodeAluRx64 op:
context.EmitLdintzr(op.Rm); context.EmitLdintzr(op.Rm);
context.EmitCast(op.IntType); context.EmitCast(op.IntType);
context.EmitLsl(op.Shift); context.EmitLsl(op.Shift);
@ -178,9 +178,9 @@ namespace ChocolArm64.Instructions
public static void EmitDataStore(ILEmitterCtx context, bool setFlags) public static void EmitDataStore(ILEmitterCtx context, bool setFlags)
{ {
IOpCodeAlu op = (IOpCodeAlu)context.CurrOp; IOpCodeAlu64 op = (IOpCodeAlu64)context.CurrOp;
if (setFlags || op is IOpCodeAluRs) if (setFlags || op is IOpCodeAluRs64)
{ {
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
} }

16
ChocolArm64/Instructions/InstEmitBfm.cs
View file

@ -9,7 +9,7 @@ namespace ChocolArm64.Instructions
{ {
public static void Bfm(ILEmitterCtx context) public static void Bfm(ILEmitterCtx context)
{ {
OpCodeBfm op = (OpCodeBfm)context.CurrOp; OpCodeBfm64 op = (OpCodeBfm64)context.CurrOp;
EmitBfmLoadRn(context); EmitBfmLoadRn(context);
@ -30,7 +30,7 @@ namespace ChocolArm64.Instructions
public static void Sbfm(ILEmitterCtx context) public static void Sbfm(ILEmitterCtx context)
{ {
OpCodeBfm op = (OpCodeBfm)context.CurrOp; OpCodeBfm64 op = (OpCodeBfm64)context.CurrOp;
int bitsCount = op.GetBitsCount(); int bitsCount = op.GetBitsCount();
@ -74,7 +74,7 @@ namespace ChocolArm64.Instructions
public static void Ubfm(ILEmitterCtx context) public static void Ubfm(ILEmitterCtx context)
{ {
OpCodeBfm op = (OpCodeBfm)context.CurrOp; OpCodeBfm64 op = (OpCodeBfm64)context.CurrOp;
if (op.Pos + 1 == op.GetBitsCount()) if (op.Pos + 1 == op.GetBitsCount())
{ {
@ -109,7 +109,7 @@ namespace ChocolArm64.Instructions
private static void EmitBfiz(ILEmitterCtx context, bool signed) private static void EmitBfiz(ILEmitterCtx context, bool signed)
{ {
OpCodeBfm op = (OpCodeBfm)context.CurrOp; OpCodeBfm64 op = (OpCodeBfm64)context.CurrOp;
int width = op.Pos + 1; int width = op.Pos + 1;
@ -141,7 +141,7 @@ namespace ChocolArm64.Instructions
private static void EmitBfmCast(ILEmitterCtx context, OpCode ilOp, bool signed) private static void EmitBfmCast(ILEmitterCtx context, OpCode ilOp, bool signed)
{ {
OpCodeBfm op = (OpCodeBfm)context.CurrOp; OpCodeBfm64 op = (OpCodeBfm64)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
@ -169,7 +169,7 @@ namespace ChocolArm64.Instructions
private static void EmitBfmShift(ILEmitterCtx context, bool signed) private static void EmitBfmShift(ILEmitterCtx context, bool signed)
{ {
OpCodeBfm op = (OpCodeBfm)context.CurrOp; OpCodeBfm64 op = (OpCodeBfm64)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
context.EmitLdc_I4(op.Shift); context.EmitLdc_I4(op.Shift);
@ -183,7 +183,7 @@ namespace ChocolArm64.Instructions
private static void EmitBfmLsl(ILEmitterCtx context) private static void EmitBfmLsl(ILEmitterCtx context)
{ {
OpCodeBfm op = (OpCodeBfm)context.CurrOp; OpCodeBfm64 op = (OpCodeBfm64)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
@ -194,7 +194,7 @@ namespace ChocolArm64.Instructions
private static void EmitBfmLoadRn(ILEmitterCtx context) private static void EmitBfmLoadRn(ILEmitterCtx context)
{ {
OpCodeBfm op = (OpCodeBfm)context.CurrOp; OpCodeBfm64 op = (OpCodeBfm64)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);

2
ChocolArm64/Instructions/InstEmitCcmp.cs
View file

@ -21,7 +21,7 @@ namespace ChocolArm64.Instructions
private static void EmitCcmp(ILEmitterCtx context, CcmpOp cmpOp) private static void EmitCcmp(ILEmitterCtx context, CcmpOp cmpOp)
{ {
OpCodeCcmp op = (OpCodeCcmp)context.CurrOp; OpCodeCcmp64 op = (OpCodeCcmp64)context.CurrOp;
ILLabel lblTrue = new ILLabel(); ILLabel lblTrue = new ILLabel();
ILLabel lblEnd = new ILLabel(); ILLabel lblEnd = new ILLabel();

2
ChocolArm64/Instructions/InstEmitCsel.cs
View file

@ -21,7 +21,7 @@ namespace ChocolArm64.Instructions
private static void EmitCsel(ILEmitterCtx context, CselOperation cselOp) private static void EmitCsel(ILEmitterCtx context, CselOperation cselOp)
{ {
OpCodeCsel op = (OpCodeCsel)context.CurrOp; OpCodeCsel64 op = (OpCodeCsel64)context.CurrOp;
ILLabel lblTrue = new ILLabel(); ILLabel lblTrue = new ILLabel();
ILLabel lblEnd = new ILLabel(); ILLabel lblEnd = new ILLabel();

4
ChocolArm64/Instructions/InstEmitException.cs
View file

@ -19,7 +19,7 @@ namespace ChocolArm64.Instructions
private static void EmitExceptionCall(ILEmitterCtx context, string mthdName) private static void EmitExceptionCall(ILEmitterCtx context, string mthdName)
{ {
OpCodeException op = (OpCodeException)context.CurrOp; OpCodeException64 op = (OpCodeException64)context.CurrOp;
context.EmitStoreState(); context.EmitStoreState();
@ -60,7 +60,7 @@ namespace ChocolArm64.Instructions
public static void Und(ILEmitterCtx context) public static void Und(ILEmitterCtx context)
{ {
AOpCode op = context.CurrOp; OpCode64 op = context.CurrOp;
context.EmitStoreState(); context.EmitStoreState();

18
ChocolArm64/Instructions/InstEmitFlow.cs
View file

@ -9,7 +9,7 @@ namespace ChocolArm64.Instructions
{ {
public static void B(ILEmitterCtx context) public static void B(ILEmitterCtx context)
{ {
OpCodeBImmAl op = (OpCodeBImmAl)context.CurrOp; OpCodeBImmAl64 op = (OpCodeBImmAl64)context.CurrOp;
if (context.CurrBlock.Branch != null) if (context.CurrBlock.Branch != null)
{ {
@ -26,14 +26,14 @@ namespace ChocolArm64.Instructions
public static void B_Cond(ILEmitterCtx context) public static void B_Cond(ILEmitterCtx context)
{ {
OpCodeBImmCond op = (OpCodeBImmCond)context.CurrOp; OpCodeBImmCond64 op = (OpCodeBImmCond64)context.CurrOp;
EmitBranch(context, op.Cond); EmitBranch(context, op.Cond);
} }
public static void Bl(ILEmitterCtx context) public static void Bl(ILEmitterCtx context)
{ {
OpCodeBImmAl op = (OpCodeBImmAl)context.CurrOp; OpCodeBImmAl64 op = (OpCodeBImmAl64)context.CurrOp;
context.EmitLdc_I(op.Position + 4); context.EmitLdc_I(op.Position + 4);
context.EmitStint(CpuThreadState.LrIndex); context.EmitStint(CpuThreadState.LrIndex);
@ -70,7 +70,7 @@ namespace ChocolArm64.Instructions
public static void Blr(ILEmitterCtx context) public static void Blr(ILEmitterCtx context)
{ {
OpCodeBReg op = (OpCodeBReg)context.CurrOp; OpCodeBReg64 op = (OpCodeBReg64)context.CurrOp;
context.EmitLdc_I(op.Position + 4); context.EmitLdc_I(op.Position + 4);
context.EmitStint(CpuThreadState.LrIndex); context.EmitStint(CpuThreadState.LrIndex);
@ -82,7 +82,7 @@ namespace ChocolArm64.Instructions
public static void Br(ILEmitterCtx context) public static void Br(ILEmitterCtx context)
{ {
OpCodeBReg op = (OpCodeBReg)context.CurrOp; OpCodeBReg64 op = (OpCodeBReg64)context.CurrOp;
context.EmitStoreState(); context.EmitStoreState();
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
@ -95,7 +95,7 @@ namespace ChocolArm64.Instructions
private static void EmitCb(ILEmitterCtx context, OpCode ilOp) private static void EmitCb(ILEmitterCtx context, OpCode ilOp)
{ {
OpCodeBImmCmp op = (OpCodeBImmCmp)context.CurrOp; OpCodeBImmCmp64 op = (OpCodeBImmCmp64)context.CurrOp;
context.EmitLdintzr(op.Rt); context.EmitLdintzr(op.Rt);
context.EmitLdc_I(0); context.EmitLdc_I(0);
@ -116,7 +116,7 @@ namespace ChocolArm64.Instructions
private static void EmitTb(ILEmitterCtx context, OpCode ilOp) private static void EmitTb(ILEmitterCtx context, OpCode ilOp)
{ {
OpCodeBImmTest op = (OpCodeBImmTest)context.CurrOp; OpCodeBImmTest64 op = (OpCodeBImmTest64)context.CurrOp;
context.EmitLdintzr(op.Rt); context.EmitLdintzr(op.Rt);
context.EmitLdc_I(1L << op.Pos); context.EmitLdc_I(1L << op.Pos);
@ -130,7 +130,7 @@ namespace ChocolArm64.Instructions
private static void EmitBranch(ILEmitterCtx context, Cond cond) private static void EmitBranch(ILEmitterCtx context, Cond cond)
{ {
OpCodeBImm op = (OpCodeBImm)context.CurrOp; OpCodeBImm64 op = (OpCodeBImm64)context.CurrOp;
if (context.CurrBlock.Next != null && if (context.CurrBlock.Next != null &&
context.CurrBlock.Branch != null) context.CurrBlock.Branch != null)
@ -159,7 +159,7 @@ namespace ChocolArm64.Instructions
private static void EmitBranch(ILEmitterCtx context, OpCode ilOp) private static void EmitBranch(ILEmitterCtx context, OpCode ilOp)
{ {
OpCodeBImm op = (OpCodeBImm)context.CurrOp; OpCodeBImm64 op = (OpCodeBImm64)context.CurrOp;
if (context.CurrBlock.Next != null && if (context.CurrBlock.Next != null &&
context.CurrBlock.Branch != null) context.CurrBlock.Branch != null)

4
ChocolArm64/Instructions/InstEmitHash.cs
View file

@ -79,7 +79,7 @@ namespace ChocolArm64.Instructions
private static void EmitSse42Crc32(ILEmitterCtx context, Type tCrc, Type tData) private static void EmitSse42Crc32(ILEmitterCtx context, Type tCrc, Type tData)
{ {
OpCodeAluRs op = (OpCodeAluRs)context.CurrOp; OpCodeAluRs64 op = (OpCodeAluRs64)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
context.EmitLdintzr(op.Rm); context.EmitLdintzr(op.Rm);
@ -91,7 +91,7 @@ namespace ChocolArm64.Instructions
private static void EmitCrc32(ILEmitterCtx context, string name) private static void EmitCrc32(ILEmitterCtx context, string name)
{ {
OpCodeAluRs op = (OpCodeAluRs)context.CurrOp; OpCodeAluRs64 op = (OpCodeAluRs64)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);

32
ChocolArm64/Instructions/InstEmitMemory.cs
View file

@ -10,7 +10,7 @@ namespace ChocolArm64.Instructions
{ {
public static void Adr(ILEmitterCtx context) public static void Adr(ILEmitterCtx context)
{ {
OpCodeAdr op = (OpCodeAdr)context.CurrOp; OpCodeAdr64 op = (OpCodeAdr64)context.CurrOp;
context.EmitLdc_I(op.Position + op.Imm); context.EmitLdc_I(op.Position + op.Imm);
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
@ -18,7 +18,7 @@ namespace ChocolArm64.Instructions
public static void Adrp(ILEmitterCtx context) public static void Adrp(ILEmitterCtx context)
{ {
OpCodeAdr op = (OpCodeAdr)context.CurrOp; OpCodeAdr64 op = (OpCodeAdr64)context.CurrOp;
context.EmitLdc_I((op.Position & ~0xfffL) + (op.Imm << 12)); context.EmitLdc_I((op.Position & ~0xfffL) + (op.Imm << 12));
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
@ -29,7 +29,7 @@ namespace ChocolArm64.Instructions
private static void EmitLdr(ILEmitterCtx context, bool signed) private static void EmitLdr(ILEmitterCtx context, bool signed)
{ {
OpCodeMem op = (OpCodeMem)context.CurrOp; OpCodeMem64 op = (OpCodeMem64)context.CurrOp;
context.EmitLdarg(TranslatedSub.MemoryArgIdx); context.EmitLdarg(TranslatedSub.MemoryArgIdx);
@ -48,7 +48,7 @@ namespace ChocolArm64.Instructions
EmitReadZxCall(context, op.Size); EmitReadZxCall(context, op.Size);
} }
if (op is IOpCodeSimd) if (op is IOpCodeSimd64)
{ {
context.EmitStvec(op.Rt); context.EmitStvec(op.Rt);
} }
@ -62,7 +62,7 @@ namespace ChocolArm64.Instructions
public static void LdrLit(ILEmitterCtx context) public static void LdrLit(ILEmitterCtx context)
{ {
IOpCodeLit op = (IOpCodeLit)context.CurrOp; IOpCodeLit64 op = (IOpCodeLit64)context.CurrOp;
if (op.Prefetch) if (op.Prefetch)
{ {
@ -81,7 +81,7 @@ namespace ChocolArm64.Instructions
EmitReadZxCall(context, op.Size); EmitReadZxCall(context, op.Size);
} }
if (op is IOpCodeSimd) if (op is IOpCodeSimd64)
{ {
context.EmitStvec(op.Rt); context.EmitStvec(op.Rt);
} }
@ -93,7 +93,7 @@ namespace ChocolArm64.Instructions
public static void Ldp(ILEmitterCtx context) public static void Ldp(ILEmitterCtx context)
{ {
OpCodeMemPair op = (OpCodeMemPair)context.CurrOp; OpCodeMemPair64 op = (OpCodeMemPair64)context.CurrOp;
void EmitReadAndStore(int rt) void EmitReadAndStore(int rt)
{ {
@ -106,7 +106,7 @@ namespace ChocolArm64.Instructions
EmitReadZxCall(context, op.Size); EmitReadZxCall(context, op.Size);
} }
if (op is IOpCodeSimd) if (op is IOpCodeSimd64)
{ {
context.EmitStvec(rt); context.EmitStvec(rt);
} }
@ -135,13 +135,13 @@ namespace ChocolArm64.Instructions
public static void Str(ILEmitterCtx context) public static void Str(ILEmitterCtx context)
{ {
OpCodeMem op = (OpCodeMem)context.CurrOp; OpCodeMem64 op = (OpCodeMem64)context.CurrOp;
context.EmitLdarg(TranslatedSub.MemoryArgIdx); context.EmitLdarg(TranslatedSub.MemoryArgIdx);
EmitLoadAddress(context); EmitLoadAddress(context);
if (op is IOpCodeSimd) if (op is IOpCodeSimd64)
{ {
context.EmitLdvec(op.Rt); context.EmitLdvec(op.Rt);
} }
@ -157,13 +157,13 @@ namespace ChocolArm64.Instructions
public static void Stp(ILEmitterCtx context) public static void Stp(ILEmitterCtx context)
{ {
OpCodeMemPair op = (OpCodeMemPair)context.CurrOp; OpCodeMemPair64 op = (OpCodeMemPair64)context.CurrOp;
context.EmitLdarg(TranslatedSub.MemoryArgIdx); context.EmitLdarg(TranslatedSub.MemoryArgIdx);
EmitLoadAddress(context); EmitLoadAddress(context);
if (op is IOpCodeSimd) if (op is IOpCodeSimd64)
{ {
context.EmitLdvec(op.Rt); context.EmitLdvec(op.Rt);
} }
@ -180,7 +180,7 @@ namespace ChocolArm64.Instructions
context.Emit(OpCodes.Add); context.Emit(OpCodes.Add);
if (op is IOpCodeSimd) if (op is IOpCodeSimd64)
{ {
context.EmitLdvec(op.Rt2); context.EmitLdvec(op.Rt2);
} }
@ -198,7 +198,7 @@ namespace ChocolArm64.Instructions
{ {
switch (context.CurrOp) switch (context.CurrOp)
{ {
case OpCodeMemImm op: case OpCodeMemImm64 op:
context.EmitLdint(op.Rn); context.EmitLdint(op.Rn);
if (!op.PostIdx) if (!op.PostIdx)
@ -210,7 +210,7 @@ namespace ChocolArm64.Instructions
} }
break; break;
case OpCodeMemReg op: case OpCodeMemReg64 op:
context.EmitLdint(op.Rn); context.EmitLdint(op.Rn);
context.EmitLdintzr(op.Rm); context.EmitLdintzr(op.Rm);
context.EmitCast(op.IntType); context.EmitCast(op.IntType);
@ -234,7 +234,7 @@ namespace ChocolArm64.Instructions
{ {
//Check whenever the current OpCode has post-indexed write back, if so write it. //Check whenever the current OpCode has post-indexed write back, if so write it.
//Note: AOpCodeMemPair inherits from AOpCodeMemImm, so this works for both. //Note: AOpCodeMemPair inherits from AOpCodeMemImm, so this works for both.
if (context.CurrOp is OpCodeMemImm op && op.WBack) if (context.CurrOp is OpCodeMemImm64 op && op.WBack)
{ {
context.EmitLdtmp(); context.EmitLdtmp();

4
ChocolArm64/Instructions/InstEmitMemoryEx.cs
View file

@ -47,7 +47,7 @@ namespace ChocolArm64.Instructions
private static void EmitLoad(ILEmitterCtx context, AccessType accType, bool pair) private static void EmitLoad(ILEmitterCtx context, AccessType accType, bool pair)
{ {
OpCodeMemEx op = (OpCodeMemEx)context.CurrOp; OpCodeMemEx64 op = (OpCodeMemEx64)context.CurrOp;
bool ordered = (accType & AccessType.Ordered) != 0; bool ordered = (accType & AccessType.Ordered) != 0;
bool exclusive = (accType & AccessType.Exclusive) != 0; bool exclusive = (accType & AccessType.Exclusive) != 0;
@ -109,7 +109,7 @@ namespace ChocolArm64.Instructions
private static void EmitStore(ILEmitterCtx context, AccessType accType, bool pair) private static void EmitStore(ILEmitterCtx context, AccessType accType, bool pair)
{ {
OpCodeMemEx op = (OpCodeMemEx)context.CurrOp; OpCodeMemEx64 op = (OpCodeMemEx64)context.CurrOp;
bool ordered = (accType & AccessType.Ordered) != 0; bool ordered = (accType & AccessType.Ordered) != 0;
bool exclusive = (accType & AccessType.Exclusive) != 0; bool exclusive = (accType & AccessType.Exclusive) != 0;

6
ChocolArm64/Instructions/InstEmitMemoryHelper.cs
View file

@ -130,9 +130,9 @@ namespace ChocolArm64.Instructions
private static bool GetIsSimd(ILEmitterCtx context) private static bool GetIsSimd(ILEmitterCtx context)
{ {
return context.CurrOp is IOpCodeSimd && return context.CurrOp is IOpCodeSimd64 &&
!(context.CurrOp is OpCodeSimdMemMs || !(context.CurrOp is OpCodeSimdMemMs64 ||
context.CurrOp is OpCodeSimdMemSs); context.CurrOp is OpCodeSimdMemSs64);
} }
} }
} }

6
ChocolArm64/Instructions/InstEmitMove.cs
View file

@ -8,7 +8,7 @@ namespace ChocolArm64.Instructions
{ {
public static void Movk(ILEmitterCtx context) public static void Movk(ILEmitterCtx context)
{ {
OpCodeMov op = (OpCodeMov)context.CurrOp; OpCodeMov64 op = (OpCodeMov64)context.CurrOp;
context.EmitLdintzr(op.Rd); context.EmitLdintzr(op.Rd);
context.EmitLdc_I(~(0xffffL << op.Pos)); context.EmitLdc_I(~(0xffffL << op.Pos));
@ -24,7 +24,7 @@ namespace ChocolArm64.Instructions
public static void Movn(ILEmitterCtx context) public static void Movn(ILEmitterCtx context)
{ {
OpCodeMov op = (OpCodeMov)context.CurrOp; OpCodeMov64 op = (OpCodeMov64)context.CurrOp;
context.EmitLdc_I(~op.Imm); context.EmitLdc_I(~op.Imm);
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
@ -32,7 +32,7 @@ namespace ChocolArm64.Instructions
public static void Movz(ILEmitterCtx context) public static void Movz(ILEmitterCtx context)
{ {
OpCodeMov op = (OpCodeMov)context.CurrOp; OpCodeMov64 op = (OpCodeMov64)context.CurrOp;
context.EmitLdc_I(op.Imm); context.EmitLdc_I(op.Imm);
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);

8
ChocolArm64/Instructions/InstEmitMul.cs
View file

@ -11,7 +11,7 @@ namespace ChocolArm64.Instructions
private static void EmitMul(ILEmitterCtx context, OpCode ilOp) private static void EmitMul(ILEmitterCtx context, OpCode ilOp)
{ {
OpCodeMul op = (OpCodeMul)context.CurrOp; OpCodeMul64 op = (OpCodeMul64)context.CurrOp;
context.EmitLdintzr(op.Ra); context.EmitLdintzr(op.Ra);
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
@ -30,7 +30,7 @@ namespace ChocolArm64.Instructions
private static void EmitMull(ILEmitterCtx context, OpCode addSubOp, bool signed) private static void EmitMull(ILEmitterCtx context, OpCode addSubOp, bool signed)
{ {
OpCodeMul op = (OpCodeMul)context.CurrOp; OpCodeMul64 op = (OpCodeMul64)context.CurrOp;
OpCode castOp = signed OpCode castOp = signed
? OpCodes.Conv_I8 ? OpCodes.Conv_I8
@ -55,7 +55,7 @@ namespace ChocolArm64.Instructions
public static void Smulh(ILEmitterCtx context) public static void Smulh(ILEmitterCtx context)
{ {
OpCodeMul op = (OpCodeMul)context.CurrOp; OpCodeMul64 op = (OpCodeMul64)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
context.EmitLdintzr(op.Rm); context.EmitLdintzr(op.Rm);
@ -67,7 +67,7 @@ namespace ChocolArm64.Instructions
public static void Umulh(ILEmitterCtx context) public static void Umulh(ILEmitterCtx context)
{ {
OpCodeMul op = (OpCodeMul)context.CurrOp; OpCodeMul64 op = (OpCodeMul64)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
context.EmitLdintzr(op.Rm); context.EmitLdintzr(op.Rm);

76
ChocolArm64/Instructions/InstEmitSimdArithmetic.cs
View file

@ -49,7 +49,7 @@ namespace ChocolArm64.Instructions
public static void Addp_S(ILEmitterCtx context) public static void Addp_S(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
EmitVectorExtractZx(context, op.Rn, 0, op.Size); EmitVectorExtractZx(context, op.Rn, 0, op.Size);
EmitVectorExtractZx(context, op.Rn, 1, op.Size); EmitVectorExtractZx(context, op.Rn, 1, op.Size);
@ -66,7 +66,7 @@ namespace ChocolArm64.Instructions
public static void Addv_V(ILEmitterCtx context) public static void Addv_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int bytes = op.GetBitsCount() >> 3; int bytes = op.GetBitsCount() >> 3;
int elems = bytes >> op.Size; int elems = bytes >> op.Size;
@ -85,7 +85,7 @@ namespace ChocolArm64.Instructions
public static void Cls_V(ILEmitterCtx context) public static void Cls_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int bytes = op.GetBitsCount() >> 3; int bytes = op.GetBitsCount() >> 3;
int elems = bytes >> op.Size; int elems = bytes >> op.Size;
@ -111,7 +111,7 @@ namespace ChocolArm64.Instructions
public static void Clz_V(ILEmitterCtx context) public static void Clz_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int bytes = op.GetBitsCount() >> 3; int bytes = op.GetBitsCount() >> 3;
int elems = bytes >> op.Size; int elems = bytes >> op.Size;
@ -148,7 +148,7 @@ namespace ChocolArm64.Instructions
public static void Cnt_V(ILEmitterCtx context) public static void Cnt_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int elems = op.RegisterSize == RegisterSize.Simd128 ? 16 : 8; int elems = op.RegisterSize == RegisterSize.Simd128 ? 16 : 8;
@ -234,7 +234,7 @@ namespace ChocolArm64.Instructions
public static void Faddp_S(ILEmitterCtx context) public static void Faddp_S(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -287,7 +287,7 @@ namespace ChocolArm64.Instructions
{ {
if (Optimizations.FastFP && Optimizations.UseSse2) if (Optimizations.FastFP && Optimizations.UseSse2)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
if (op.Size == 0) if (op.Size == 0)
{ {
@ -499,7 +499,7 @@ namespace ChocolArm64.Instructions
{ {
if (Optimizations.FastFP && Optimizations.UseSse2) if (Optimizations.FastFP && Optimizations.UseSse2)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
if (op.Size == 0) if (op.Size == 0)
{ {
@ -627,7 +627,7 @@ namespace ChocolArm64.Instructions
public static void Fnmadd_S(ILEmitterCtx context) public static void Fnmadd_S(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -648,7 +648,7 @@ namespace ChocolArm64.Instructions
public static void Fnmsub_S(ILEmitterCtx context) public static void Fnmsub_S(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -693,7 +693,7 @@ namespace ChocolArm64.Instructions
{ {
if (Optimizations.FastFP && Optimizations.UseSse2) if (Optimizations.FastFP && Optimizations.UseSse2)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -747,7 +747,7 @@ namespace ChocolArm64.Instructions
{ {
if (Optimizations.FastFP && Optimizations.UseSse2) if (Optimizations.FastFP && Optimizations.UseSse2)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -808,7 +808,7 @@ namespace ChocolArm64.Instructions
public static void Frinta_S(ILEmitterCtx context) public static void Frinta_S(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
EmitVectorExtractF(context, op.Rn, 0, op.Size); EmitVectorExtractF(context, op.Rn, 0, op.Size);
@ -827,7 +827,7 @@ namespace ChocolArm64.Instructions
public static void Frinti_S(ILEmitterCtx context) public static void Frinti_S(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
EmitScalarUnaryOpF(context, () => EmitScalarUnaryOpF(context, () =>
{ {
@ -850,7 +850,7 @@ namespace ChocolArm64.Instructions
public static void Frinti_V(ILEmitterCtx context) public static void Frinti_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -891,7 +891,7 @@ namespace ChocolArm64.Instructions
public static void Frintn_S(ILEmitterCtx context) public static void Frintn_S(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
EmitVectorExtractF(context, op.Rn, 0, op.Size); EmitVectorExtractF(context, op.Rn, 0, op.Size);
@ -926,7 +926,7 @@ namespace ChocolArm64.Instructions
public static void Frintx_S(ILEmitterCtx context) public static void Frintx_S(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
EmitScalarUnaryOpF(context, () => EmitScalarUnaryOpF(context, () =>
{ {
@ -949,7 +949,7 @@ namespace ChocolArm64.Instructions
public static void Frintx_V(ILEmitterCtx context) public static void Frintx_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
EmitVectorUnaryOpF(context, () => EmitVectorUnaryOpF(context, () =>
{ {
@ -990,7 +990,7 @@ namespace ChocolArm64.Instructions
{ {
if (Optimizations.FastFP && Optimizations.UseSse2) if (Optimizations.FastFP && Optimizations.UseSse2)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -1052,7 +1052,7 @@ namespace ChocolArm64.Instructions
{ {
if (Optimizations.FastFP && Optimizations.UseSse2) if (Optimizations.FastFP && Optimizations.UseSse2)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -1290,7 +1290,7 @@ namespace ChocolArm64.Instructions
{ {
if (Optimizations.UseSse41) if (Optimizations.UseSse41)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
Type[] typesSrl = new Type[] { VectorIntTypesPerSizeLog2[op.Size], typeof(byte) }; Type[] typesSrl = new Type[] { VectorIntTypesPerSizeLog2[op.Size], typeof(byte) };
Type[] typesCvt = new Type[] { VectorIntTypesPerSizeLog2[op.Size] }; Type[] typesCvt = new Type[] { VectorIntTypesPerSizeLog2[op.Size] };
@ -1339,7 +1339,7 @@ namespace ChocolArm64.Instructions
public static void Shadd_V(ILEmitterCtx context) public static void Shadd_V(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
if (Optimizations.UseSse2 && op.Size > 0) if (Optimizations.UseSse2 && op.Size > 0)
{ {
@ -1389,7 +1389,7 @@ namespace ChocolArm64.Instructions
public static void Shsub_V(ILEmitterCtx context) public static void Shsub_V(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
if (Optimizations.UseSse2 && op.Size < 2) if (Optimizations.UseSse2 && op.Size < 2)
{ {
@ -1475,7 +1475,7 @@ namespace ChocolArm64.Instructions
public static void Smlal_V(ILEmitterCtx context) public static void Smlal_V(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
if (Optimizations.UseSse41 && op.Size < 2) if (Optimizations.UseSse41 && op.Size < 2)
{ {
@ -1526,7 +1526,7 @@ namespace ChocolArm64.Instructions
public static void Smlsl_V(ILEmitterCtx context) public static void Smlsl_V(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
if (Optimizations.UseSse41 && op.Size < 2) if (Optimizations.UseSse41 && op.Size < 2)
{ {
@ -1662,7 +1662,7 @@ namespace ChocolArm64.Instructions
public static void Srhadd_V(ILEmitterCtx context) public static void Srhadd_V(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
if (Optimizations.UseSse2 && op.Size < 2) if (Optimizations.UseSse2 && op.Size < 2)
{ {
@ -1715,7 +1715,7 @@ namespace ChocolArm64.Instructions
{ {
if (Optimizations.UseSse41) if (Optimizations.UseSse41)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
Type[] typesSrl = new Type[] { VectorIntTypesPerSizeLog2[op.Size], typeof(byte) }; Type[] typesSrl = new Type[] { VectorIntTypesPerSizeLog2[op.Size], typeof(byte) };
Type[] typesCvt = new Type[] { VectorIntTypesPerSizeLog2[op.Size] }; Type[] typesCvt = new Type[] { VectorIntTypesPerSizeLog2[op.Size] };
@ -1838,7 +1838,7 @@ namespace ChocolArm64.Instructions
{ {
if (Optimizations.UseSse41) if (Optimizations.UseSse41)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
Type[] typesSrl = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) }; Type[] typesSrl = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) };
Type[] typesCvt = new Type[] { VectorUIntTypesPerSizeLog2[op.Size] }; Type[] typesCvt = new Type[] { VectorUIntTypesPerSizeLog2[op.Size] };
@ -1882,7 +1882,7 @@ namespace ChocolArm64.Instructions
public static void Uaddlv_V(ILEmitterCtx context) public static void Uaddlv_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int bytes = op.GetBitsCount() >> 3; int bytes = op.GetBitsCount() >> 3;
int elems = bytes >> op.Size; int elems = bytes >> op.Size;
@ -1906,7 +1906,7 @@ namespace ChocolArm64.Instructions
public static void Uhadd_V(ILEmitterCtx context) public static void Uhadd_V(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
if (Optimizations.UseSse2 && op.Size > 0) if (Optimizations.UseSse2 && op.Size > 0)
{ {
@ -1956,7 +1956,7 @@ namespace ChocolArm64.Instructions
public static void Uhsub_V(ILEmitterCtx context) public static void Uhsub_V(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
if (Optimizations.UseSse2 && op.Size < 2) if (Optimizations.UseSse2 && op.Size < 2)
{ {
@ -2028,7 +2028,7 @@ namespace ChocolArm64.Instructions
public static void Umlal_V(ILEmitterCtx context) public static void Umlal_V(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
if (Optimizations.UseSse41 && op.Size < 2) if (Optimizations.UseSse41 && op.Size < 2)
{ {
@ -2079,7 +2079,7 @@ namespace ChocolArm64.Instructions
public static void Umlsl_V(ILEmitterCtx context) public static void Umlsl_V(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
if (Optimizations.UseSse41 && op.Size < 2) if (Optimizations.UseSse41 && op.Size < 2)
{ {
@ -2165,7 +2165,7 @@ namespace ChocolArm64.Instructions
public static void Urhadd_V(ILEmitterCtx context) public static void Urhadd_V(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
if (Optimizations.UseSse2 && op.Size < 2) if (Optimizations.UseSse2 && op.Size < 2)
{ {
@ -2212,7 +2212,7 @@ namespace ChocolArm64.Instructions
{ {
if (Optimizations.UseSse41) if (Optimizations.UseSse41)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
Type[] typesSrl = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) }; Type[] typesSrl = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) };
Type[] typesCvt = new Type[] { VectorUIntTypesPerSizeLog2[op.Size] }; Type[] typesCvt = new Type[] { VectorUIntTypesPerSizeLog2[op.Size] };
@ -2269,7 +2269,7 @@ namespace ChocolArm64.Instructions
private static void EmitAddLongPairwise(ILEmitterCtx context, bool signed, bool accumulate) private static void EmitAddLongPairwise(ILEmitterCtx context, bool signed, bool accumulate)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int words = op.GetBitsCount() >> 4; int words = op.GetBitsCount() >> 4;
int pairs = words >> op.Size; int pairs = words >> op.Size;
@ -2304,7 +2304,7 @@ namespace ChocolArm64.Instructions
private static void EmitDoublingMultiplyHighHalf(ILEmitterCtx context, bool round) private static void EmitDoublingMultiplyHighHalf(ILEmitterCtx context, bool round)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int eSize = 8 << op.Size; int eSize = 8 << op.Size;
@ -2340,7 +2340,7 @@ namespace ChocolArm64.Instructions
private static void EmitHighNarrow(ILEmitterCtx context, Action emit, bool round) private static void EmitHighNarrow(ILEmitterCtx context, Action emit, bool round)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int elems = 8 >> op.Size; int elems = 8 >> op.Size;

36
ChocolArm64/Instructions/InstEmitSimdCmp.cs
View file

@ -19,7 +19,7 @@ namespace ChocolArm64.Instructions
public static void Cmeq_V(ILEmitterCtx context) public static void Cmeq_V(ILEmitterCtx context)
{ {
if (context.CurrOp is OpCodeSimdReg op) if (context.CurrOp is OpCodeSimdReg64 op)
{ {
if (op.Size < 3 && Optimizations.UseSse2) if (op.Size < 3 && Optimizations.UseSse2)
{ {
@ -57,7 +57,7 @@ namespace ChocolArm64.Instructions
public static void Cmgt_V(ILEmitterCtx context) public static void Cmgt_V(ILEmitterCtx context)
{ {
if (context.CurrOp is OpCodeSimdReg op) if (context.CurrOp is OpCodeSimdReg64 op)
{ {
if (op.Size < 3 && Optimizations.UseSse2) if (op.Size < 3 && Optimizations.UseSse2)
{ {
@ -130,7 +130,7 @@ namespace ChocolArm64.Instructions
public static void Fccmp_S(ILEmitterCtx context) public static void Fccmp_S(ILEmitterCtx context)
{ {
OpCodeSimdFcond op = (OpCodeSimdFcond)context.CurrOp; OpCodeSimdFcond64 op = (OpCodeSimdFcond64)context.CurrOp;
ILLabel lblTrue = new ILLabel(); ILLabel lblTrue = new ILLabel();
ILLabel lblEnd = new ILLabel(); ILLabel lblEnd = new ILLabel();
@ -155,7 +155,7 @@ namespace ChocolArm64.Instructions
public static void Fcmeq_S(ILEmitterCtx context) public static void Fcmeq_S(ILEmitterCtx context)
{ {
if (context.CurrOp is OpCodeSimdReg && Optimizations.UseSse if (context.CurrOp is OpCodeSimdReg64 && Optimizations.UseSse
&& Optimizations.UseSse2) && Optimizations.UseSse2)
{ {
EmitScalarSseOrSse2OpF(context, nameof(Sse.CompareEqualScalar)); EmitScalarSseOrSse2OpF(context, nameof(Sse.CompareEqualScalar));
@ -168,7 +168,7 @@ namespace ChocolArm64.Instructions
public static void Fcmeq_V(ILEmitterCtx context) public static void Fcmeq_V(ILEmitterCtx context)
{ {
if (context.CurrOp is OpCodeSimdReg && Optimizations.UseSse if (context.CurrOp is OpCodeSimdReg64 && Optimizations.UseSse
&& Optimizations.UseSse2) && Optimizations.UseSse2)
{ {
EmitVectorSseOrSse2OpF(context, nameof(Sse.CompareEqual)); EmitVectorSseOrSse2OpF(context, nameof(Sse.CompareEqual));
@ -181,7 +181,7 @@ namespace ChocolArm64.Instructions
public static void Fcmge_S(ILEmitterCtx context) public static void Fcmge_S(ILEmitterCtx context)
{ {
if (context.CurrOp is OpCodeSimdReg && Optimizations.UseSse if (context.CurrOp is OpCodeSimdReg64 && Optimizations.UseSse
&& Optimizations.UseSse2) && Optimizations.UseSse2)
{ {
EmitScalarSseOrSse2OpF(context, nameof(Sse.CompareGreaterThanOrEqualScalar)); EmitScalarSseOrSse2OpF(context, nameof(Sse.CompareGreaterThanOrEqualScalar));
@ -194,7 +194,7 @@ namespace ChocolArm64.Instructions
public static void Fcmge_V(ILEmitterCtx context) public static void Fcmge_V(ILEmitterCtx context)
{ {
if (context.CurrOp is OpCodeSimdReg && Optimizations.UseSse if (context.CurrOp is OpCodeSimdReg64 && Optimizations.UseSse
&& Optimizations.UseSse2) && Optimizations.UseSse2)
{ {
EmitVectorSseOrSse2OpF(context, nameof(Sse.CompareGreaterThanOrEqual)); EmitVectorSseOrSse2OpF(context, nameof(Sse.CompareGreaterThanOrEqual));
@ -207,7 +207,7 @@ namespace ChocolArm64.Instructions
public static void Fcmgt_S(ILEmitterCtx context) public static void Fcmgt_S(ILEmitterCtx context)
{ {
if (context.CurrOp is OpCodeSimdReg && Optimizations.UseSse if (context.CurrOp is OpCodeSimdReg64 && Optimizations.UseSse
&& Optimizations.UseSse2) && Optimizations.UseSse2)
{ {
EmitScalarSseOrSse2OpF(context, nameof(Sse.CompareGreaterThanScalar)); EmitScalarSseOrSse2OpF(context, nameof(Sse.CompareGreaterThanScalar));
@ -220,7 +220,7 @@ namespace ChocolArm64.Instructions
public static void Fcmgt_V(ILEmitterCtx context) public static void Fcmgt_V(ILEmitterCtx context)
{ {
if (context.CurrOp is OpCodeSimdReg && Optimizations.UseSse if (context.CurrOp is OpCodeSimdReg64 && Optimizations.UseSse
&& Optimizations.UseSse2) && Optimizations.UseSse2)
{ {
EmitVectorSseOrSse2OpF(context, nameof(Sse.CompareGreaterThan)); EmitVectorSseOrSse2OpF(context, nameof(Sse.CompareGreaterThan));
@ -253,9 +253,9 @@ namespace ChocolArm64.Instructions
public static void Fcmp_S(ILEmitterCtx context) public static void Fcmp_S(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
bool cmpWithZero = !(op is OpCodeSimdFcond) ? op.Bit3 : false; bool cmpWithZero = !(op is OpCodeSimdFcond64) ? op.Bit3 : false;
//Handle NaN case. //Handle NaN case.
//If any number is NaN, then NZCV = 0011. //If any number is NaN, then NZCV = 0011.
@ -341,7 +341,7 @@ namespace ChocolArm64.Instructions
private static void EmitNaNCheck(ILEmitterCtx context, int reg) private static void EmitNaNCheck(ILEmitterCtx context, int reg)
{ {
IOpCodeSimd op = (IOpCodeSimd)context.CurrOp; IOpCodeSimd64 op = (IOpCodeSimd64)context.CurrOp;
EmitVectorExtractF(context, reg, 0, op.Size); EmitVectorExtractF(context, reg, 0, op.Size);
@ -361,7 +361,7 @@ namespace ChocolArm64.Instructions
private static void EmitCmp(ILEmitterCtx context, OpCode ilOp, bool scalar) private static void EmitCmp(ILEmitterCtx context, OpCode ilOp, bool scalar)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int bytes = op.GetBitsCount() >> 3; int bytes = op.GetBitsCount() >> 3;
int elems = !scalar ? bytes >> op.Size : 1; int elems = !scalar ? bytes >> op.Size : 1;
@ -372,7 +372,7 @@ namespace ChocolArm64.Instructions
{ {
EmitVectorExtractSx(context, op.Rn, index, op.Size); EmitVectorExtractSx(context, op.Rn, index, op.Size);
if (op is OpCodeSimdReg binOp) if (op is OpCodeSimdReg64 binOp)
{ {
EmitVectorExtractSx(context, binOp.Rm, index, op.Size); EmitVectorExtractSx(context, binOp.Rm, index, op.Size);
} }
@ -405,7 +405,7 @@ namespace ChocolArm64.Instructions
private static void EmitCmtst(ILEmitterCtx context, bool scalar) private static void EmitCmtst(ILEmitterCtx context, bool scalar)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int bytes = op.GetBitsCount() >> 3; int bytes = op.GetBitsCount() >> 3;
int elems = !scalar ? bytes >> op.Size : 1; int elems = !scalar ? bytes >> op.Size : 1;
@ -450,7 +450,7 @@ namespace ChocolArm64.Instructions
private static void EmitVectorFcmp(ILEmitterCtx context, OpCode ilOp) private static void EmitVectorFcmp(ILEmitterCtx context, OpCode ilOp)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -470,7 +470,7 @@ namespace ChocolArm64.Instructions
private static void EmitFcmp(ILEmitterCtx context, OpCode ilOp, int index, bool scalar) private static void EmitFcmp(ILEmitterCtx context, OpCode ilOp, int index, bool scalar)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -478,7 +478,7 @@ namespace ChocolArm64.Instructions
EmitVectorExtractF(context, op.Rn, index, sizeF); EmitVectorExtractF(context, op.Rn, index, sizeF);
if (op is OpCodeSimdReg binOp) if (op is OpCodeSimdReg64 binOp)
{ {
EmitVectorExtractF(context, binOp.Rm, index, sizeF); EmitVectorExtractF(context, binOp.Rm, index, sizeF);
} }

8
ChocolArm64/Instructions/InstEmitSimdCrypto.cs
View file

@ -7,7 +7,7 @@ namespace ChocolArm64.Instructions
{ {
public static void Aesd_V(ILEmitterCtx context) public static void Aesd_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
context.EmitLdvec(op.Rd); context.EmitLdvec(op.Rd);
context.EmitLdvec(op.Rn); context.EmitLdvec(op.Rn);
@ -19,7 +19,7 @@ namespace ChocolArm64.Instructions
public static void Aese_V(ILEmitterCtx context) public static void Aese_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
context.EmitLdvec(op.Rd); context.EmitLdvec(op.Rd);
context.EmitLdvec(op.Rn); context.EmitLdvec(op.Rn);
@ -31,7 +31,7 @@ namespace ChocolArm64.Instructions
public static void Aesimc_V(ILEmitterCtx context) public static void Aesimc_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
context.EmitLdvec(op.Rn); context.EmitLdvec(op.Rn);
@ -42,7 +42,7 @@ namespace ChocolArm64.Instructions
public static void Aesmc_V(ILEmitterCtx context) public static void Aesmc_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
context.EmitLdvec(op.Rn); context.EmitLdvec(op.Rn);

28
ChocolArm64/Instructions/InstEmitSimdCvt.cs
View file

@ -14,7 +14,7 @@ namespace ChocolArm64.Instructions
{ {
public static void Fcvt_S(ILEmitterCtx context) public static void Fcvt_S(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
if (Optimizations.UseSse2) if (Optimizations.UseSse2)
{ {
@ -72,7 +72,7 @@ namespace ChocolArm64.Instructions
public static void Fcvtl_V(ILEmitterCtx context) public static void Fcvtl_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -117,7 +117,7 @@ namespace ChocolArm64.Instructions
public static void Fcvtn_V(ILEmitterCtx context) public static void Fcvtn_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -233,7 +233,7 @@ namespace ChocolArm64.Instructions
public static void Scvtf_Gp(ILEmitterCtx context) public static void Scvtf_Gp(ILEmitterCtx context)
{ {
OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp; OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
@ -249,7 +249,7 @@ namespace ChocolArm64.Instructions
public static void Scvtf_S(ILEmitterCtx context) public static void Scvtf_S(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
EmitVectorExtractSx(context, op.Rn, 0, op.Size + 2); EmitVectorExtractSx(context, op.Rn, 0, op.Size + 2);
@ -265,7 +265,7 @@ namespace ChocolArm64.Instructions
public static void Ucvtf_Gp(ILEmitterCtx context) public static void Ucvtf_Gp(ILEmitterCtx context)
{ {
OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp; OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
@ -283,7 +283,7 @@ namespace ChocolArm64.Instructions
public static void Ucvtf_S(ILEmitterCtx context) public static void Ucvtf_S(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
EmitVectorExtractZx(context, op.Rn, 0, op.Size + 2); EmitVectorExtractZx(context, op.Rn, 0, op.Size + 2);
@ -301,7 +301,7 @@ namespace ChocolArm64.Instructions
private static int GetFBits(ILEmitterCtx context) private static int GetFBits(ILEmitterCtx context)
{ {
if (context.CurrOp is OpCodeSimdShImm op) if (context.CurrOp is OpCodeSimdShImm64 op)
{ {
return GetImmShr(op); return GetImmShr(op);
} }
@ -327,7 +327,7 @@ namespace ChocolArm64.Instructions
private static void EmitFcvtn(ILEmitterCtx context, bool signed, bool scalar) private static void EmitFcvtn(ILEmitterCtx context, bool signed, bool scalar)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
int sizeI = sizeF + 2; int sizeI = sizeF + 2;
@ -385,7 +385,7 @@ namespace ChocolArm64.Instructions
private static void EmitFcvt___Gp(ILEmitterCtx context, Action emit, bool signed) private static void EmitFcvt___Gp(ILEmitterCtx context, Action emit, bool signed)
{ {
OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp; OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
EmitVectorExtractF(context, op.Rn, 0, op.Size); EmitVectorExtractF(context, op.Rn, 0, op.Size);
@ -420,7 +420,7 @@ namespace ChocolArm64.Instructions
private static void EmitFcvtz__Gp_Fix(ILEmitterCtx context, bool signed) private static void EmitFcvtz__Gp_Fix(ILEmitterCtx context, bool signed)
{ {
OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp; OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
EmitVectorExtractF(context, op.Rn, 0, op.Size); EmitVectorExtractF(context, op.Rn, 0, op.Size);
@ -453,7 +453,7 @@ namespace ChocolArm64.Instructions
private static void EmitVectorCvtf(ILEmitterCtx context, bool signed) private static void EmitVectorCvtf(ILEmitterCtx context, bool signed)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
int sizeI = sizeF + 2; int sizeI = sizeF + 2;
@ -499,7 +499,7 @@ namespace ChocolArm64.Instructions
private static void EmitScalarFcvtz(ILEmitterCtx context, bool signed) private static void EmitScalarFcvtz(ILEmitterCtx context, bool signed)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
int sizeI = sizeF + 2; int sizeI = sizeF + 2;
@ -543,7 +543,7 @@ namespace ChocolArm64.Instructions
private static void EmitVectorFcvtz(ILEmitterCtx context, bool signed) private static void EmitVectorFcvtz(ILEmitterCtx context, bool signed)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
int sizeI = sizeF + 2; int sizeI = sizeF + 2;

20
ChocolArm64/Instructions/InstEmitSimdHash.cs
View file

@ -10,7 +10,7 @@ namespace ChocolArm64.Instructions
#region "Sha1" #region "Sha1"
public static void Sha1c_V(ILEmitterCtx context) public static void Sha1c_V(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
context.EmitLdvec(op.Rd); context.EmitLdvec(op.Rd);
EmitVectorExtractZx(context, op.Rn, 0, 2); EmitVectorExtractZx(context, op.Rn, 0, 2);
@ -23,7 +23,7 @@ namespace ChocolArm64.Instructions
public static void Sha1h_V(ILEmitterCtx context) public static void Sha1h_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
EmitVectorExtractZx(context, op.Rn, 0, 2); EmitVectorExtractZx(context, op.Rn, 0, 2);
@ -34,7 +34,7 @@ namespace ChocolArm64.Instructions
public static void Sha1m_V(ILEmitterCtx context) public static void Sha1m_V(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
context.EmitLdvec(op.Rd); context.EmitLdvec(op.Rd);
EmitVectorExtractZx(context, op.Rn, 0, 2); EmitVectorExtractZx(context, op.Rn, 0, 2);
@ -47,7 +47,7 @@ namespace ChocolArm64.Instructions
public static void Sha1p_V(ILEmitterCtx context) public static void Sha1p_V(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
context.EmitLdvec(op.Rd); context.EmitLdvec(op.Rd);
EmitVectorExtractZx(context, op.Rn, 0, 2); EmitVectorExtractZx(context, op.Rn, 0, 2);
@ -60,7 +60,7 @@ namespace ChocolArm64.Instructions
public static void Sha1su0_V(ILEmitterCtx context) public static void Sha1su0_V(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
context.EmitLdvec(op.Rd); context.EmitLdvec(op.Rd);
context.EmitLdvec(op.Rn); context.EmitLdvec(op.Rn);
@ -73,7 +73,7 @@ namespace ChocolArm64.Instructions
public static void Sha1su1_V(ILEmitterCtx context) public static void Sha1su1_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
context.EmitLdvec(op.Rd); context.EmitLdvec(op.Rd);
context.EmitLdvec(op.Rn); context.EmitLdvec(op.Rn);
@ -87,7 +87,7 @@ namespace ChocolArm64.Instructions
#region "Sha256" #region "Sha256"
public static void Sha256h_V(ILEmitterCtx context) public static void Sha256h_V(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
context.EmitLdvec(op.Rd); context.EmitLdvec(op.Rd);
context.EmitLdvec(op.Rn); context.EmitLdvec(op.Rn);
@ -100,7 +100,7 @@ namespace ChocolArm64.Instructions
public static void Sha256h2_V(ILEmitterCtx context) public static void Sha256h2_V(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
context.EmitLdvec(op.Rd); context.EmitLdvec(op.Rd);
context.EmitLdvec(op.Rn); context.EmitLdvec(op.Rn);
@ -113,7 +113,7 @@ namespace ChocolArm64.Instructions
public static void Sha256su0_V(ILEmitterCtx context) public static void Sha256su0_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
context.EmitLdvec(op.Rd); context.EmitLdvec(op.Rd);
context.EmitLdvec(op.Rn); context.EmitLdvec(op.Rn);
@ -125,7 +125,7 @@ namespace ChocolArm64.Instructions
public static void Sha256su1_V(ILEmitterCtx context) public static void Sha256su1_V(ILEmitterCtx context)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
context.EmitLdvec(op.Rd); context.EmitLdvec(op.Rd);
context.EmitLdvec(op.Rn); context.EmitLdvec(op.Rn);

88
ChocolArm64/Instructions/InstEmitSimdHelper.cs
View file

@ -57,12 +57,12 @@ namespace ChocolArm64.Instructions
RdRnRm = Rd | Rn | Rm RdRnRm = Rd | Rn | Rm
} }
public static int GetImmShl(OpCodeSimdShImm op) public static int GetImmShl(OpCodeSimdShImm64 op)
{ {
return op.Imm - (8 << op.Size); return op.Imm - (8 << op.Size);
} }
public static int GetImmShr(OpCodeSimdShImm op) public static int GetImmShr(OpCodeSimdShImm64 op)
{ {
return (8 << (op.Size + 1)) - op.Imm; return (8 << (op.Size + 1)) - op.Imm;
} }
@ -84,13 +84,13 @@ namespace ChocolArm64.Instructions
private static void EmitSseOp(ILEmitterCtx context, string name, Type type) private static void EmitSseOp(ILEmitterCtx context, string name, Type type)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
EmitLdvecWithSignedCast(context, op.Rn, op.Size); EmitLdvecWithSignedCast(context, op.Rn, op.Size);
Type baseType = VectorIntTypesPerSizeLog2[op.Size]; Type baseType = VectorIntTypesPerSizeLog2[op.Size];
if (op is OpCodeSimdReg binOp) if (op is OpCodeSimdReg64 binOp)
{ {
EmitLdvecWithSignedCast(context, binOp.Rm, op.Size); EmitLdvecWithSignedCast(context, binOp.Rm, op.Size);
@ -195,7 +195,7 @@ namespace ChocolArm64.Instructions
public static void EmitSseOrSse2OpF(ILEmitterCtx context, string name, bool scalar) public static void EmitSseOrSse2OpF(ILEmitterCtx context, string name, bool scalar)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -225,7 +225,7 @@ namespace ChocolArm64.Instructions
baseType = typeof(Vector128<double>); baseType = typeof(Vector128<double>);
} }
if (op is OpCodeSimdReg binOp) if (op is OpCodeSimdReg64 binOp)
{ {
Ldvec(binOp.Rm); Ldvec(binOp.Rm);
@ -262,7 +262,7 @@ namespace ChocolArm64.Instructions
public static void EmitUnaryMathCall(ILEmitterCtx context, string name) public static void EmitUnaryMathCall(ILEmitterCtx context, string name)
{ {
IOpCodeSimd op = (IOpCodeSimd)context.CurrOp; IOpCodeSimd64 op = (IOpCodeSimd64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -282,7 +282,7 @@ namespace ChocolArm64.Instructions
public static void EmitBinaryMathCall(ILEmitterCtx context, string name) public static void EmitBinaryMathCall(ILEmitterCtx context, string name)
{ {
IOpCodeSimd op = (IOpCodeSimd)context.CurrOp; IOpCodeSimd64 op = (IOpCodeSimd64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -302,7 +302,7 @@ namespace ChocolArm64.Instructions
public static void EmitRoundMathCall(ILEmitterCtx context, MidpointRounding roundMode) public static void EmitRoundMathCall(ILEmitterCtx context, MidpointRounding roundMode)
{ {
IOpCodeSimd op = (IOpCodeSimd)context.CurrOp; IOpCodeSimd64 op = (IOpCodeSimd64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -324,7 +324,7 @@ namespace ChocolArm64.Instructions
public static void EmitUnarySoftFloatCall(ILEmitterCtx context, string name) public static void EmitUnarySoftFloatCall(ILEmitterCtx context, string name)
{ {
IOpCodeSimd op = (IOpCodeSimd)context.CurrOp; IOpCodeSimd64 op = (IOpCodeSimd64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -344,7 +344,7 @@ namespace ChocolArm64.Instructions
public static void EmitSoftFloatCall(ILEmitterCtx context, string name) public static void EmitSoftFloatCall(ILEmitterCtx context, string name)
{ {
IOpCodeSimd op = (IOpCodeSimd)context.CurrOp; IOpCodeSimd64 op = (IOpCodeSimd64)context.CurrOp;
Type type = (op.Size & 1) == 0 Type type = (op.Size & 1) == 0
? typeof(SoftFloat32) ? typeof(SoftFloat32)
@ -357,21 +357,21 @@ namespace ChocolArm64.Instructions
public static void EmitScalarBinaryOpByElemF(ILEmitterCtx context, Action emit) public static void EmitScalarBinaryOpByElemF(ILEmitterCtx context, Action emit)
{ {
OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp; OpCodeSimdRegElemF64 op = (OpCodeSimdRegElemF64)context.CurrOp;
EmitScalarOpByElemF(context, emit, op.Index, ternary: false); EmitScalarOpByElemF(context, emit, op.Index, ternary: false);
} }
public static void EmitScalarTernaryOpByElemF(ILEmitterCtx context, Action emit) public static void EmitScalarTernaryOpByElemF(ILEmitterCtx context, Action emit)
{ {
OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp; OpCodeSimdRegElemF64 op = (OpCodeSimdRegElemF64)context.CurrOp;
EmitScalarOpByElemF(context, emit, op.Index, ternary: true); EmitScalarOpByElemF(context, emit, op.Index, ternary: true);
} }
public static void EmitScalarOpByElemF(ILEmitterCtx context, Action emit, int elem, bool ternary) public static void EmitScalarOpByElemF(ILEmitterCtx context, Action emit, int elem, bool ternary)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -415,7 +415,7 @@ namespace ChocolArm64.Instructions
public static void EmitScalarOp(ILEmitterCtx context, Action emit, OperFlags opers, bool signed) public static void EmitScalarOp(ILEmitterCtx context, Action emit, OperFlags opers, bool signed)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
bool rd = (opers & OperFlags.Rd) != 0; bool rd = (opers & OperFlags.Rd) != 0;
bool rn = (opers & OperFlags.Rn) != 0; bool rn = (opers & OperFlags.Rn) != 0;
@ -433,7 +433,7 @@ namespace ChocolArm64.Instructions
if (rm) if (rm)
{ {
EmitVectorExtract(context, ((OpCodeSimdReg)op).Rm, 0, op.Size, signed); EmitVectorExtract(context, ((OpCodeSimdReg64)op).Rm, 0, op.Size, signed);
} }
emit(); emit();
@ -458,7 +458,7 @@ namespace ChocolArm64.Instructions
public static void EmitScalarOpF(ILEmitterCtx context, Action emit, OperFlags opers) public static void EmitScalarOpF(ILEmitterCtx context, Action emit, OperFlags opers)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -468,7 +468,7 @@ namespace ChocolArm64.Instructions
if (ra) if (ra)
{ {
EmitVectorExtractF(context, ((OpCodeSimdReg)op).Ra, 0, sizeF); EmitVectorExtractF(context, ((OpCodeSimdReg64)op).Ra, 0, sizeF);
} }
if (rn) if (rn)
@ -478,7 +478,7 @@ namespace ChocolArm64.Instructions
if (rm) if (rm)
{ {
EmitVectorExtractF(context, ((OpCodeSimdReg)op).Rm, 0, sizeF); EmitVectorExtractF(context, ((OpCodeSimdReg64)op).Rm, 0, sizeF);
} }
emit(); emit();
@ -503,7 +503,7 @@ namespace ChocolArm64.Instructions
public static void EmitVectorOpF(ILEmitterCtx context, Action emit, OperFlags opers) public static void EmitVectorOpF(ILEmitterCtx context, Action emit, OperFlags opers)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -528,7 +528,7 @@ namespace ChocolArm64.Instructions
if (rm) if (rm)
{ {
EmitVectorExtractF(context, ((OpCodeSimdReg)op).Rm, index, sizeF); EmitVectorExtractF(context, ((OpCodeSimdReg64)op).Rm, index, sizeF);
} }
emit(); emit();
@ -544,21 +544,21 @@ namespace ChocolArm64.Instructions
public static void EmitVectorBinaryOpByElemF(ILEmitterCtx context, Action emit) public static void EmitVectorBinaryOpByElemF(ILEmitterCtx context, Action emit)
{ {
OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp; OpCodeSimdRegElemF64 op = (OpCodeSimdRegElemF64)context.CurrOp;
EmitVectorOpByElemF(context, emit, op.Index, ternary: false); EmitVectorOpByElemF(context, emit, op.Index, ternary: false);
} }
public static void EmitVectorTernaryOpByElemF(ILEmitterCtx context, Action emit) public static void EmitVectorTernaryOpByElemF(ILEmitterCtx context, Action emit)
{ {
OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp; OpCodeSimdRegElemF64 op = (OpCodeSimdRegElemF64)context.CurrOp;
EmitVectorOpByElemF(context, emit, op.Index, ternary: true); EmitVectorOpByElemF(context, emit, op.Index, ternary: true);
} }
public static void EmitVectorOpByElemF(ILEmitterCtx context, Action emit, int elem, bool ternary) public static void EmitVectorOpByElemF(ILEmitterCtx context, Action emit, int elem, bool ternary)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -621,7 +621,7 @@ namespace ChocolArm64.Instructions
public static void EmitVectorOp(ILEmitterCtx context, Action emit, OperFlags opers, bool signed) public static void EmitVectorOp(ILEmitterCtx context, Action emit, OperFlags opers, bool signed)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int bytes = op.GetBitsCount() >> 3; int bytes = op.GetBitsCount() >> 3;
int elems = bytes >> op.Size; int elems = bytes >> op.Size;
@ -644,7 +644,7 @@ namespace ChocolArm64.Instructions
if (rm) if (rm)
{ {
EmitVectorExtract(context, ((OpCodeSimdReg)op).Rm, index, op.Size, signed); EmitVectorExtract(context, ((OpCodeSimdReg64)op).Rm, index, op.Size, signed);
} }
emit(); emit();
@ -660,28 +660,28 @@ namespace ChocolArm64.Instructions
public static void EmitVectorBinaryOpByElemSx(ILEmitterCtx context, Action emit) public static void EmitVectorBinaryOpByElemSx(ILEmitterCtx context, Action emit)
{ {
OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp; OpCodeSimdRegElem64 op = (OpCodeSimdRegElem64)context.CurrOp;
EmitVectorOpByElem(context, emit, op.Index, false, true); EmitVectorOpByElem(context, emit, op.Index, false, true);
} }
public static void EmitVectorBinaryOpByElemZx(ILEmitterCtx context, Action emit) public static void EmitVectorBinaryOpByElemZx(ILEmitterCtx context, Action emit)
{ {
OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp; OpCodeSimdRegElem64 op = (OpCodeSimdRegElem64)context.CurrOp;
EmitVectorOpByElem(context, emit, op.Index, false, false); EmitVectorOpByElem(context, emit, op.Index, false, false);
} }
public static void EmitVectorTernaryOpByElemZx(ILEmitterCtx context, Action emit) public static void EmitVectorTernaryOpByElemZx(ILEmitterCtx context, Action emit)
{ {
OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp; OpCodeSimdRegElem64 op = (OpCodeSimdRegElem64)context.CurrOp;
EmitVectorOpByElem(context, emit, op.Index, true, false); EmitVectorOpByElem(context, emit, op.Index, true, false);
} }
public static void EmitVectorOpByElem(ILEmitterCtx context, Action emit, int elem, bool ternary, bool signed) public static void EmitVectorOpByElem(ILEmitterCtx context, Action emit, int elem, bool ternary, bool signed)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int bytes = op.GetBitsCount() >> 3; int bytes = op.GetBitsCount() >> 3;
int elems = bytes >> op.Size; int elems = bytes >> op.Size;
@ -725,7 +725,7 @@ namespace ChocolArm64.Instructions
public static void EmitVectorImmOp(ILEmitterCtx context, Action emit, bool binary) public static void EmitVectorImmOp(ILEmitterCtx context, Action emit, bool binary)
{ {
OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp; OpCodeSimdImm64 op = (OpCodeSimdImm64)context.CurrOp;
int bytes = op.GetBitsCount() >> 3; int bytes = op.GetBitsCount() >> 3;
int elems = bytes >> op.Size; int elems = bytes >> op.Size;
@ -762,7 +762,7 @@ namespace ChocolArm64.Instructions
public static void EmitVectorWidenRmBinaryOp(ILEmitterCtx context, Action emit, bool signed) public static void EmitVectorWidenRmBinaryOp(ILEmitterCtx context, Action emit, bool signed)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int elems = 8 >> op.Size; int elems = 8 >> op.Size;
@ -804,7 +804,7 @@ namespace ChocolArm64.Instructions
public static void EmitVectorWidenRnRmOp(ILEmitterCtx context, Action emit, bool ternary, bool signed) public static void EmitVectorWidenRnRmOp(ILEmitterCtx context, Action emit, bool ternary, bool signed)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int elems = 8 >> op.Size; int elems = 8 >> op.Size;
@ -841,7 +841,7 @@ namespace ChocolArm64.Instructions
public static void EmitVectorPairwiseOp(ILEmitterCtx context, Action emit, bool signed) public static void EmitVectorPairwiseOp(ILEmitterCtx context, Action emit, bool signed)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int words = op.GetBitsCount() >> 4; int words = op.GetBitsCount() >> 4;
int pairs = words >> op.Size; int pairs = words >> op.Size;
@ -875,7 +875,7 @@ namespace ChocolArm64.Instructions
public static void EmitVectorPairwiseOpF(ILEmitterCtx context, Action emit) public static void EmitVectorPairwiseOpF(ILEmitterCtx context, Action emit)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int sizeF = op.Size & 1; int sizeF = op.Size & 1;
@ -939,7 +939,7 @@ namespace ChocolArm64.Instructions
public static void EmitSaturatingUnaryOpSx(ILEmitterCtx context, Action emit, SaturatingFlags flags) public static void EmitSaturatingUnaryOpSx(ILEmitterCtx context, Action emit, SaturatingFlags flags)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
bool scalar = (flags & SaturatingFlags.Scalar) != 0; bool scalar = (flags & SaturatingFlags.Scalar) != 0;
@ -1000,7 +1000,7 @@ namespace ChocolArm64.Instructions
public static void EmitSaturatingBinaryOp(ILEmitterCtx context, Action emit, SaturatingFlags flags) public static void EmitSaturatingBinaryOp(ILEmitterCtx context, Action emit, SaturatingFlags flags)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
bool scalar = (flags & SaturatingFlags.Scalar) != 0; bool scalar = (flags & SaturatingFlags.Scalar) != 0;
bool signed = (flags & SaturatingFlags.Signed) != 0; bool signed = (flags & SaturatingFlags.Signed) != 0;
@ -1023,7 +1023,7 @@ namespace ChocolArm64.Instructions
for (int index = 0; index < elems; index++) for (int index = 0; index < elems; index++)
{ {
EmitVectorExtract(context, op.Rn, index, op.Size, signed); EmitVectorExtract(context, op.Rn, index, op.Size, signed);
EmitVectorExtract(context, ((OpCodeSimdReg)op).Rm, index, op.Size, signed); EmitVectorExtract(context, ((OpCodeSimdReg64)op).Rm, index, op.Size, signed);
if (op.Size <= 2) if (op.Size <= 2)
{ {
@ -1072,7 +1072,7 @@ namespace ChocolArm64.Instructions
for (int index = 0; index < elems; index++) for (int index = 0; index < elems; index++)
{ {
EmitVectorExtract(context, op.Rn, index, op.Size, signed); EmitVectorExtract(context, op.Rn, index, op.Size, signed);
EmitVectorExtract(context, ((OpCodeSimdReg)op).Rm, index, op.Size, signed); EmitVectorExtract(context, ((OpCodeSimdReg64)op).Rm, index, op.Size, signed);
emit(); emit();
@ -1109,7 +1109,7 @@ namespace ChocolArm64.Instructions
public static void EmitSaturatingNarrowOp(ILEmitterCtx context, SaturatingNarrowFlags flags) public static void EmitSaturatingNarrowOp(ILEmitterCtx context, SaturatingNarrowFlags flags)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
bool scalar = (flags & SaturatingNarrowFlags.Scalar) != 0; bool scalar = (flags & SaturatingNarrowFlags.Scalar) != 0;
bool signedSrc = (flags & SaturatingNarrowFlags.SignedSrc) != 0; bool signedSrc = (flags & SaturatingNarrowFlags.SignedSrc) != 0;
@ -1180,7 +1180,7 @@ namespace ChocolArm64.Instructions
// TSrc (64bit) == TDst (64bit); signed. // TSrc (64bit) == TDst (64bit); signed.
public static void EmitUnarySignedSatQAbsOrNeg(ILEmitterCtx context) public static void EmitUnarySignedSatQAbsOrNeg(ILEmitterCtx context)
{ {
if (((OpCodeSimd)context.CurrOp).Size < 3) if (((OpCodeSimd64)context.CurrOp).Size < 3)
{ {
throw new InvalidOperationException(); throw new InvalidOperationException();
} }
@ -1193,7 +1193,7 @@ namespace ChocolArm64.Instructions
// TSrcs (64bit) == TDst (64bit); signed, unsigned. // TSrcs (64bit) == TDst (64bit); signed, unsigned.
public static void EmitBinarySatQAdd(ILEmitterCtx context, bool signed) public static void EmitBinarySatQAdd(ILEmitterCtx context, bool signed)
{ {
if (((OpCodeSimdReg)context.CurrOp).Size < 3) if (((OpCodeSimdReg64)context.CurrOp).Size < 3)
{ {
throw new InvalidOperationException(); throw new InvalidOperationException();
} }
@ -1208,7 +1208,7 @@ namespace ChocolArm64.Instructions
// TSrcs (64bit) == TDst (64bit); signed, unsigned. // TSrcs (64bit) == TDst (64bit); signed, unsigned.
public static void EmitBinarySatQSub(ILEmitterCtx context, bool signed) public static void EmitBinarySatQSub(ILEmitterCtx context, bool signed)
{ {
if (((OpCodeSimdReg)context.CurrOp).Size < 3) if (((OpCodeSimdReg64)context.CurrOp).Size < 3)
{ {
throw new InvalidOperationException(); throw new InvalidOperationException();
} }
@ -1223,7 +1223,7 @@ namespace ChocolArm64.Instructions
// TSrcs (64bit) == TDst (64bit); signed, unsigned. // TSrcs (64bit) == TDst (64bit); signed, unsigned.
public static void EmitBinarySatQAccumulate(ILEmitterCtx context, bool signed) public static void EmitBinarySatQAccumulate(ILEmitterCtx context, bool signed)
{ {
if (((OpCodeSimd)context.CurrOp).Size < 3) if (((OpCodeSimd64)context.CurrOp).Size < 3)
{ {
throw new InvalidOperationException(); throw new InvalidOperationException();
} }

10
ChocolArm64/Instructions/InstEmitSimdLogical.cs
View file

@ -27,7 +27,7 @@ namespace ChocolArm64.Instructions
{ {
if (Optimizations.UseSse2) if (Optimizations.UseSse2)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
EmitLdvecWithUnsignedCast(context, op.Rm, op.Size); EmitLdvecWithUnsignedCast(context, op.Rm, op.Size);
EmitLdvecWithUnsignedCast(context, op.Rn, op.Size); EmitLdvecWithUnsignedCast(context, op.Rn, op.Size);
@ -78,7 +78,7 @@ namespace ChocolArm64.Instructions
private static void EmitBitBif(ILEmitterCtx context, bool notRm) private static void EmitBitBif(ILEmitterCtx context, bool notRm)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
if (Optimizations.UseSse2) if (Optimizations.UseSse2)
{ {
@ -148,7 +148,7 @@ namespace ChocolArm64.Instructions
{ {
if (Optimizations.UseSse2) if (Optimizations.UseSse2)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
Type[] types = new Type[] Type[] types = new Type[]
{ {
@ -238,7 +238,7 @@ namespace ChocolArm64.Instructions
public static void Rbit_V(ILEmitterCtx context) public static void Rbit_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int elems = op.RegisterSize == RegisterSize.Simd128 ? 16 : 8; int elems = op.RegisterSize == RegisterSize.Simd128 ? 16 : 8;
@ -278,7 +278,7 @@ namespace ChocolArm64.Instructions
private static void EmitRev_V(ILEmitterCtx context, int containerSize) private static void EmitRev_V(ILEmitterCtx context, int containerSize)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
if (op.Size >= containerSize) if (op.Size >= containerSize)
{ {

6
ChocolArm64/Instructions/InstEmitSimdMemory.cs
View file

@ -33,7 +33,7 @@ namespace ChocolArm64.Instructions
private static void EmitSimdMemMs(ILEmitterCtx context, bool isLoad) private static void EmitSimdMemMs(ILEmitterCtx context, bool isLoad)
{ {
OpCodeSimdMemMs op = (OpCodeSimdMemMs)context.CurrOp; OpCodeSimdMemMs64 op = (OpCodeSimdMemMs64)context.CurrOp;
int offset = 0; int offset = 0;
@ -84,7 +84,7 @@ namespace ChocolArm64.Instructions
private static void EmitSimdMemSs(ILEmitterCtx context, bool isLoad) private static void EmitSimdMemSs(ILEmitterCtx context, bool isLoad)
{ {
OpCodeSimdMemSs op = (OpCodeSimdMemSs)context.CurrOp; OpCodeSimdMemSs64 op = (OpCodeSimdMemSs64)context.CurrOp;
int offset = 0; int offset = 0;
@ -164,7 +164,7 @@ namespace ChocolArm64.Instructions
private static void EmitSimdMemWBack(ILEmitterCtx context, int offset) private static void EmitSimdMemWBack(ILEmitterCtx context, int offset)
{ {
OpCodeMemReg op = (OpCodeMemReg)context.CurrOp; OpCodeMemReg64 op = (OpCodeMemReg64)context.CurrOp;
context.EmitLdint(op.Rn); context.EmitLdint(op.Rn);

42
ChocolArm64/Instructions/InstEmitSimdMove.cs
View file

@ -13,7 +13,7 @@ namespace ChocolArm64.Instructions
{ {
public static void Dup_Gp(ILEmitterCtx context) public static void Dup_Gp(ILEmitterCtx context)
{ {
OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp; OpCodeSimdIns64 op = (OpCodeSimdIns64)context.CurrOp;
if (Optimizations.UseSse2) if (Optimizations.UseSse2)
{ {
@ -58,7 +58,7 @@ namespace ChocolArm64.Instructions
public static void Dup_S(ILEmitterCtx context) public static void Dup_S(ILEmitterCtx context)
{ {
OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp; OpCodeSimdIns64 op = (OpCodeSimdIns64)context.CurrOp;
EmitVectorExtractZx(context, op.Rn, op.DstIndex, op.Size); EmitVectorExtractZx(context, op.Rn, op.DstIndex, op.Size);
@ -67,7 +67,7 @@ namespace ChocolArm64.Instructions
public static void Dup_V(ILEmitterCtx context) public static void Dup_V(ILEmitterCtx context)
{ {
OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp; OpCodeSimdIns64 op = (OpCodeSimdIns64)context.CurrOp;
int bytes = op.GetBitsCount() >> 3; int bytes = op.GetBitsCount() >> 3;
int elems = bytes >> op.Size; int elems = bytes >> op.Size;
@ -87,7 +87,7 @@ namespace ChocolArm64.Instructions
public static void Ext_V(ILEmitterCtx context) public static void Ext_V(ILEmitterCtx context)
{ {
OpCodeSimdExt op = (OpCodeSimdExt)context.CurrOp; OpCodeSimdExt64 op = (OpCodeSimdExt64)context.CurrOp;
context.EmitLdvec(op.Rd); context.EmitLdvec(op.Rd);
context.EmitStvectmp(); context.EmitStvectmp();
@ -120,7 +120,7 @@ namespace ChocolArm64.Instructions
public static void Fcsel_S(ILEmitterCtx context) public static void Fcsel_S(ILEmitterCtx context)
{ {
OpCodeSimdFcond op = (OpCodeSimdFcond)context.CurrOp; OpCodeSimdFcond64 op = (OpCodeSimdFcond64)context.CurrOp;
ILLabel lblTrue = new ILLabel(); ILLabel lblTrue = new ILLabel();
ILLabel lblEnd = new ILLabel(); ILLabel lblEnd = new ILLabel();
@ -142,7 +142,7 @@ namespace ChocolArm64.Instructions
public static void Fmov_Ftoi(ILEmitterCtx context) public static void Fmov_Ftoi(ILEmitterCtx context)
{ {
OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp; OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
EmitVectorExtractZx(context, op.Rn, 0, 3); EmitVectorExtractZx(context, op.Rn, 0, 3);
@ -153,7 +153,7 @@ namespace ChocolArm64.Instructions
public static void Fmov_Ftoi1(ILEmitterCtx context) public static void Fmov_Ftoi1(ILEmitterCtx context)
{ {
OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp; OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
EmitVectorExtractZx(context, op.Rn, 1, 3); EmitVectorExtractZx(context, op.Rn, 1, 3);
@ -164,7 +164,7 @@ namespace ChocolArm64.Instructions
public static void Fmov_Itof(ILEmitterCtx context) public static void Fmov_Itof(ILEmitterCtx context)
{ {
OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp; OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
@ -175,7 +175,7 @@ namespace ChocolArm64.Instructions
public static void Fmov_Itof1(ILEmitterCtx context) public static void Fmov_Itof1(ILEmitterCtx context)
{ {
OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp; OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
@ -186,7 +186,7 @@ namespace ChocolArm64.Instructions
public static void Fmov_S(ILEmitterCtx context) public static void Fmov_S(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
EmitVectorExtractF(context, op.Rn, 0, op.Size); EmitVectorExtractF(context, op.Rn, 0, op.Size);
@ -195,7 +195,7 @@ namespace ChocolArm64.Instructions
public static void Fmov_Si(ILEmitterCtx context) public static void Fmov_Si(ILEmitterCtx context)
{ {
OpCodeSimdFmov op = (OpCodeSimdFmov)context.CurrOp; OpCodeSimdFmov64 op = (OpCodeSimdFmov64)context.CurrOp;
context.EmitLdc_I8(op.Imm); context.EmitLdc_I8(op.Imm);
@ -204,7 +204,7 @@ namespace ChocolArm64.Instructions
public static void Fmov_V(ILEmitterCtx context) public static void Fmov_V(ILEmitterCtx context)
{ {
OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp; OpCodeSimdImm64 op = (OpCodeSimdImm64)context.CurrOp;
int elems = op.RegisterSize == RegisterSize.Simd128 ? 4 : 2; int elems = op.RegisterSize == RegisterSize.Simd128 ? 4 : 2;
@ -223,7 +223,7 @@ namespace ChocolArm64.Instructions
public static void Ins_Gp(ILEmitterCtx context) public static void Ins_Gp(ILEmitterCtx context)
{ {
OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp; OpCodeSimdIns64 op = (OpCodeSimdIns64)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
@ -232,7 +232,7 @@ namespace ChocolArm64.Instructions
public static void Ins_V(ILEmitterCtx context) public static void Ins_V(ILEmitterCtx context)
{ {
OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp; OpCodeSimdIns64 op = (OpCodeSimdIns64)context.CurrOp;
EmitVectorExtractZx(context, op.Rn, op.SrcIndex, op.Size); EmitVectorExtractZx(context, op.Rn, op.SrcIndex, op.Size);
@ -251,7 +251,7 @@ namespace ChocolArm64.Instructions
public static void Smov_S(ILEmitterCtx context) public static void Smov_S(ILEmitterCtx context)
{ {
OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp; OpCodeSimdIns64 op = (OpCodeSimdIns64)context.CurrOp;
EmitVectorExtractSx(context, op.Rn, op.DstIndex, op.Size); EmitVectorExtractSx(context, op.Rn, op.DstIndex, op.Size);
@ -262,7 +262,7 @@ namespace ChocolArm64.Instructions
public static void Tbl_V(ILEmitterCtx context) public static void Tbl_V(ILEmitterCtx context)
{ {
OpCodeSimdTbl op = (OpCodeSimdTbl)context.CurrOp; OpCodeSimdTbl64 op = (OpCodeSimdTbl64)context.CurrOp;
context.EmitLdvec(op.Rm); context.EmitLdvec(op.Rm);
@ -307,7 +307,7 @@ namespace ChocolArm64.Instructions
public static void Umov_S(ILEmitterCtx context) public static void Umov_S(ILEmitterCtx context)
{ {
OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp; OpCodeSimdIns64 op = (OpCodeSimdIns64)context.CurrOp;
EmitVectorExtractZx(context, op.Rn, op.DstIndex, op.Size); EmitVectorExtractZx(context, op.Rn, op.DstIndex, op.Size);
@ -326,7 +326,7 @@ namespace ChocolArm64.Instructions
public static void Xtn_V(ILEmitterCtx context) public static void Xtn_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int elems = 8 >> op.Size; int elems = 8 >> op.Size;
@ -442,7 +442,7 @@ namespace ChocolArm64.Instructions
private static void EmitVectorTranspose(ILEmitterCtx context, int part) private static void EmitVectorTranspose(ILEmitterCtx context, int part)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int words = op.GetBitsCount() >> 4; int words = op.GetBitsCount() >> 4;
int pairs = words >> op.Size; int pairs = words >> op.Size;
@ -469,7 +469,7 @@ namespace ChocolArm64.Instructions
private static void EmitVectorUnzip(ILEmitterCtx context, int part) private static void EmitVectorUnzip(ILEmitterCtx context, int part)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
int words = op.GetBitsCount() >> 4; int words = op.GetBitsCount() >> 4;
int pairs = words >> op.Size; int pairs = words >> op.Size;
@ -496,7 +496,7 @@ namespace ChocolArm64.Instructions
private static void EmitVectorZip(ILEmitterCtx context, int part) private static void EmitVectorZip(ILEmitterCtx context, int part)
{ {
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
if (Optimizations.UseSse2) if (Optimizations.UseSse2)
{ {

38
ChocolArm64/Instructions/InstEmitSimdShift.cs
View file

@ -20,7 +20,7 @@ namespace ChocolArm64.Instructions
public static void Shl_S(ILEmitterCtx context) public static void Shl_S(ILEmitterCtx context)
{ {
OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; OpCodeSimdShImm64 op = (OpCodeSimdShImm64)context.CurrOp;
EmitScalarUnaryOpZx(context, () => EmitScalarUnaryOpZx(context, () =>
{ {
@ -32,7 +32,7 @@ namespace ChocolArm64.Instructions
public static void Shl_V(ILEmitterCtx context) public static void Shl_V(ILEmitterCtx context)
{ {
OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; OpCodeSimdShImm64 op = (OpCodeSimdShImm64)context.CurrOp;
if (Optimizations.UseSse2 && op.Size > 0) if (Optimizations.UseSse2 && op.Size > 0)
{ {
@ -63,7 +63,7 @@ namespace ChocolArm64.Instructions
public static void Shll_V(ILEmitterCtx context) public static void Shll_V(ILEmitterCtx context)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int shift = 8 << op.Size; int shift = 8 << op.Size;
@ -77,7 +77,7 @@ namespace ChocolArm64.Instructions
public static void Sli_V(ILEmitterCtx context) public static void Sli_V(ILEmitterCtx context)
{ {
OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; OpCodeSimdShImm64 op = (OpCodeSimdShImm64)context.CurrOp;
int bytes = op.GetBitsCount() >> 3; int bytes = op.GetBitsCount() >> 3;
int elems = bytes >> op.Size; int elems = bytes >> op.Size;
@ -157,7 +157,7 @@ namespace ChocolArm64.Instructions
public static void Srshr_V(ILEmitterCtx context) public static void Srshr_V(ILEmitterCtx context)
{ {
OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; OpCodeSimdShImm64 op = (OpCodeSimdShImm64)context.CurrOp;
if (Optimizations.UseSse2 && op.Size > 0 if (Optimizations.UseSse2 && op.Size > 0
&& op.Size < 3) && op.Size < 3)
@ -206,7 +206,7 @@ namespace ChocolArm64.Instructions
public static void Srsra_V(ILEmitterCtx context) public static void Srsra_V(ILEmitterCtx context)
{ {
OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; OpCodeSimdShImm64 op = (OpCodeSimdShImm64)context.CurrOp;
if (Optimizations.UseSse2 && op.Size > 0 if (Optimizations.UseSse2 && op.Size > 0
&& op.Size < 3) && op.Size < 3)
@ -257,7 +257,7 @@ namespace ChocolArm64.Instructions
public static void Sshll_V(ILEmitterCtx context) public static void Sshll_V(ILEmitterCtx context)
{ {
OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; OpCodeSimdShImm64 op = (OpCodeSimdShImm64)context.CurrOp;
EmitVectorShImmWidenBinarySx(context, () => context.Emit(OpCodes.Shl), GetImmShl(op)); EmitVectorShImmWidenBinarySx(context, () => context.Emit(OpCodes.Shl), GetImmShl(op));
} }
@ -269,7 +269,7 @@ namespace ChocolArm64.Instructions
public static void Sshr_V(ILEmitterCtx context) public static void Sshr_V(ILEmitterCtx context)
{ {
OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; OpCodeSimdShImm64 op = (OpCodeSimdShImm64)context.CurrOp;
if (Optimizations.UseSse2 && op.Size > 0 if (Optimizations.UseSse2 && op.Size > 0
&& op.Size < 3) && op.Size < 3)
@ -301,7 +301,7 @@ namespace ChocolArm64.Instructions
public static void Ssra_V(ILEmitterCtx context) public static void Ssra_V(ILEmitterCtx context)
{ {
OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; OpCodeSimdShImm64 op = (OpCodeSimdShImm64)context.CurrOp;
if (Optimizations.UseSse2 && op.Size > 0 if (Optimizations.UseSse2 && op.Size > 0
&& op.Size < 3) && op.Size < 3)
@ -357,7 +357,7 @@ namespace ChocolArm64.Instructions
public static void Urshr_V(ILEmitterCtx context) public static void Urshr_V(ILEmitterCtx context)
{ {
OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; OpCodeSimdShImm64 op = (OpCodeSimdShImm64)context.CurrOp;
if (Optimizations.UseSse2 && op.Size > 0) if (Optimizations.UseSse2 && op.Size > 0)
{ {
@ -405,7 +405,7 @@ namespace ChocolArm64.Instructions
public static void Ursra_V(ILEmitterCtx context) public static void Ursra_V(ILEmitterCtx context)
{ {
OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; OpCodeSimdShImm64 op = (OpCodeSimdShImm64)context.CurrOp;
if (Optimizations.UseSse2 && op.Size > 0) if (Optimizations.UseSse2 && op.Size > 0)
{ {
@ -455,7 +455,7 @@ namespace ChocolArm64.Instructions
public static void Ushll_V(ILEmitterCtx context) public static void Ushll_V(ILEmitterCtx context)
{ {
OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; OpCodeSimdShImm64 op = (OpCodeSimdShImm64)context.CurrOp;
EmitVectorShImmWidenBinaryZx(context, () => context.Emit(OpCodes.Shl), GetImmShl(op)); EmitVectorShImmWidenBinaryZx(context, () => context.Emit(OpCodes.Shl), GetImmShl(op));
} }
@ -467,7 +467,7 @@ namespace ChocolArm64.Instructions
public static void Ushr_V(ILEmitterCtx context) public static void Ushr_V(ILEmitterCtx context)
{ {
OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; OpCodeSimdShImm64 op = (OpCodeSimdShImm64)context.CurrOp;
if (Optimizations.UseSse2 && op.Size > 0) if (Optimizations.UseSse2 && op.Size > 0)
{ {
@ -498,7 +498,7 @@ namespace ChocolArm64.Instructions
public static void Usra_V(ILEmitterCtx context) public static void Usra_V(ILEmitterCtx context)
{ {
OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; OpCodeSimdShImm64 op = (OpCodeSimdShImm64)context.CurrOp;
if (Optimizations.UseSse2 && op.Size > 0) if (Optimizations.UseSse2 && op.Size > 0)
{ {
@ -532,7 +532,7 @@ namespace ChocolArm64.Instructions
//specified on the signed, lower 8 bits of vector B. If the shift value //specified on the signed, lower 8 bits of vector B. If the shift value
//is greater or equal to the data size of each lane, then the result is zero. //is greater or equal to the data size of each lane, then the result is zero.
//Additionally, negative shifts produces right shifts by the negated shift value. //Additionally, negative shifts produces right shifts by the negated shift value.
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int maxShift = 8 << op.Size; int maxShift = 8 << op.Size;
@ -627,7 +627,7 @@ namespace ChocolArm64.Instructions
private static void EmitShrImmOp(ILEmitterCtx context, ShrImmFlags flags) private static void EmitShrImmOp(ILEmitterCtx context, ShrImmFlags flags)
{ {
OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; OpCodeSimdShImm64 op = (OpCodeSimdShImm64)context.CurrOp;
bool scalar = (flags & ShrImmFlags.Scalar) != 0; bool scalar = (flags & ShrImmFlags.Scalar) != 0;
bool signed = (flags & ShrImmFlags.Signed) != 0; bool signed = (flags & ShrImmFlags.Signed) != 0;
@ -684,7 +684,7 @@ namespace ChocolArm64.Instructions
private static void EmitVectorShrImmNarrowOpZx(ILEmitterCtx context, bool round) private static void EmitVectorShrImmNarrowOpZx(ILEmitterCtx context, bool round)
{ {
OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; OpCodeSimdShImm64 op = (OpCodeSimdShImm64)context.CurrOp;
int shift = GetImmShr(op); int shift = GetImmShr(op);
@ -752,7 +752,7 @@ namespace ChocolArm64.Instructions
private static void EmitShrImmSaturatingNarrowOp(ILEmitterCtx context, ShrImmSaturatingNarrowFlags flags) private static void EmitShrImmSaturatingNarrowOp(ILEmitterCtx context, ShrImmSaturatingNarrowFlags flags)
{ {
OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; OpCodeSimdShImm64 op = (OpCodeSimdShImm64)context.CurrOp;
bool scalar = (flags & ShrImmSaturatingNarrowFlags.Scalar) != 0; bool scalar = (flags & ShrImmSaturatingNarrowFlags.Scalar) != 0;
bool signedSrc = (flags & ShrImmSaturatingNarrowFlags.SignedSrc) != 0; bool signedSrc = (flags & ShrImmSaturatingNarrowFlags.SignedSrc) != 0;
@ -841,7 +841,7 @@ namespace ChocolArm64.Instructions
private static void EmitVectorShImmWidenBinaryOp(ILEmitterCtx context, Action emit, int imm, bool signed) private static void EmitVectorShImmWidenBinaryOp(ILEmitterCtx context, Action emit, int imm, bool signed)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
int elems = 8 >> op.Size; int elems = 8 >> op.Size;

8
ChocolArm64/Instructions/InstEmitSystem.cs
View file

@ -21,7 +21,7 @@ namespace ChocolArm64.Instructions
public static void Mrs(ILEmitterCtx context) public static void Mrs(ILEmitterCtx context)
{ {
OpCodeSystem op = (OpCodeSystem)context.CurrOp; OpCodeSystem64 op = (OpCodeSystem64)context.CurrOp;
context.EmitLdarg(TranslatedSub.StateArgIdx); context.EmitLdarg(TranslatedSub.StateArgIdx);
@ -56,7 +56,7 @@ namespace ChocolArm64.Instructions
public static void Msr(ILEmitterCtx context) public static void Msr(ILEmitterCtx context)
{ {
OpCodeSystem op = (OpCodeSystem)context.CurrOp; OpCodeSystem64 op = (OpCodeSystem64)context.CurrOp;
context.EmitLdarg(TranslatedSub.StateArgIdx); context.EmitLdarg(TranslatedSub.StateArgIdx);
context.EmitLdintzr(op.Rt); context.EmitLdintzr(op.Rt);
@ -93,7 +93,7 @@ namespace ChocolArm64.Instructions
//This instruction is used to do some operations on the CPU like cache invalidation, //This instruction is used to do some operations on the CPU like cache invalidation,
//address translation and the like. //address translation and the like.
//We treat it as no-op here since we don't have any cache being emulated anyway. //We treat it as no-op here since we don't have any cache being emulated anyway.
OpCodeSystem op = (OpCodeSystem)context.CurrOp; OpCodeSystem64 op = (OpCodeSystem64)context.CurrOp;
switch (GetPackedId(op)) switch (GetPackedId(op))
{ {
@ -122,7 +122,7 @@ namespace ChocolArm64.Instructions
} }
} }
private static int GetPackedId(OpCodeSystem op) private static int GetPackedId(OpCodeSystem64 op)
{ {
int id; int id;

2
ChocolArm64/Instructions/InstInterpreter.cs
View file

@ -4,5 +4,5 @@ using ChocolArm64.State;
namespace ChocolArm64.Instructions namespace ChocolArm64.Instructions
{ {
delegate void InstInterpreter(CpuThreadState state, MemoryManager memory, AOpCode opCode); delegate void InstInterpreter(CpuThreadState state, MemoryManager memory, OpCode64 opCode);
} }

8
ChocolArm64/Instructions32/A32InstInterpretFlow.cs
View file

@ -9,7 +9,7 @@ namespace ChocolArm64.Instructions32
{ {
static partial class A32InstInterpret static partial class A32InstInterpret
{ {
public static void B(CpuThreadState state, MemoryManager memory, AOpCode opCode) public static void B(CpuThreadState state, MemoryManager memory, OpCode64 opCode)
{ {
A32OpCodeBImmAl op = (A32OpCodeBImmAl)opCode; A32OpCodeBImmAl op = (A32OpCodeBImmAl)opCode;
@ -19,17 +19,17 @@ namespace ChocolArm64.Instructions32
} }
} }
public static void Bl(CpuThreadState state, MemoryManager memory, AOpCode opCode) public static void Bl(CpuThreadState state, MemoryManager memory, OpCode64 opCode)
{ {
Blx(state, memory, opCode, false); Blx(state, memory, opCode, false);
} }
public static void Blx(CpuThreadState state, MemoryManager memory, AOpCode opCode) public static void Blx(CpuThreadState state, MemoryManager memory, OpCode64 opCode)
{ {
Blx(state, memory, opCode, true); Blx(state, memory, opCode, true);
} }
public static void Blx(CpuThreadState state, MemoryManager memory, AOpCode opCode, bool x) public static void Blx(CpuThreadState state, MemoryManager memory, OpCode64 opCode, bool x)
{ {
A32OpCodeBImmAl op = (A32OpCodeBImmAl)opCode; A32OpCodeBImmAl op = (A32OpCodeBImmAl)opCode;

1020
ChocolArm64/OpCodeTable.cs
View file

File diff suppressed because it is too large Load diff

8
ChocolArm64/Translation/ILEmitterCtx.cs
View file

@ -20,14 +20,14 @@ namespace ChocolArm64.Translation
private Block[] _graph; private Block[] _graph;
private Block _root; private Block _root;
public Block CurrBlock => _graph[_blkIndex]; public Block CurrBlock => _graph[_blkIndex];
public AOpCode CurrOp => _graph[_blkIndex].OpCodes[_opcIndex]; public OpCode64 CurrOp => _graph[_blkIndex].OpCodes[_opcIndex];
private ILEmitter _emitter; private ILEmitter _emitter;
private ILBlock _ilBlock; private ILBlock _ilBlock;
private AOpCode _optOpLastCompare; private OpCode64 _optOpLastCompare;
private AOpCode _optOpLastFlagSet; private OpCode64 _optOpLastFlagSet;
//This is the index of the temporary register, used to store temporary //This is the index of the temporary register, used to store temporary
//values needed by some functions, since IL doesn't have a swap instruction. //values needed by some functions, since IL doesn't have a swap instruction.
@ -138,7 +138,7 @@ namespace ChocolArm64.Translation
return false; return false;
} }
if (!_cache.TryGetSubroutine(((OpCodeBImmAl)CurrOp).Imm, out TranslatedSub subroutine)) if (!_cache.TryGetSubroutine(((OpCodeBImmAl64)CurrOp).Imm, out TranslatedSub subroutine))
{ {
return false; return false;
} }

4
ChocolArm64/Translator.cs
View file

@ -43,7 +43,7 @@ namespace ChocolArm64
{ {
do do
{ {
AOpCode opCode = Decoder.DecodeOpCode(state, memory, state.R15); OpCode64 opCode = Decoder.DecodeOpCode(state, memory, state.R15);
opCode.Interpreter(state, memory, opCode); opCode.Interpreter(state, memory, opCode);
} }
@ -101,7 +101,7 @@ namespace ChocolArm64
_cache.AddOrUpdate(position, subroutine, block.OpCodes.Count); _cache.AddOrUpdate(position, subroutine, block.OpCodes.Count);
AOpCode lastOp = block.GetLastOp(); OpCode64 lastOp = block.GetLastOp();
return subroutine; return subroutine;
} }