mirrors/Ryujinx
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Update AInstEmitSimdHelper.cs

Browse source
This commit is contained in:
LDj3SNuD 2018-07-14 21:05:58 +02:00 • committed by GitHub
commit c5d76ee79a
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 11 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

12
ChocolArm64/Instruction/AInstEmitSimdHelper.cs
View file

@ -813,6 +813,7 @@ namespace ChocolArm64.Instruction
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
int Elems = !Scalar ? 8 >> Op.Size : 1; int Elems = !Scalar ? 8 >> Op.Size : 1;
int ESize = 8 << Op.Size; int ESize = 8 << Op.Size;
int Part = !Scalar && (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0; int Part = !Scalar && (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0;
@ -823,6 +824,12 @@ namespace ChocolArm64.Instruction
Context.EmitLdc_I8(0L); Context.EmitLdc_I8(0L);
Context.EmitSttmp(); Context.EmitSttmp();
if (Part != 0)
{
Context.EmitLdvec(Op.Rd);
Context.EmitStvectmp();
}
for (int Index = 0; Index < Elems; Index++) for (int Index = 0; Index < Elems; Index++)
{ {
AILLabel LblLe = new AILLabel(); AILLabel LblLe = new AILLabel();
@ -867,9 +874,12 @@ namespace ChocolArm64.Instruction
EmitVectorZeroLower(Context, Op.Rd); EmitVectorZeroLower(Context, Op.Rd);
} }
EmitVectorInsert(Context, Op.Rd, Part + Index, Op.Size); EmitVectorInsertTmp(Context, Part + Index, Op.Size);
} }
Context.EmitLdvectmp();
Context.EmitStvec(Op.Rd);
if (Part == 0) if (Part == 0)
{ {
EmitVectorZeroUpper(Context, Op.Rd); EmitVectorZeroUpper(Context, Op.Rd);