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Create AInstEmitSimdHash.cs

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LDj3SNuD 2018-08-15 02:27:35 +02:00 • committed by GitHub
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commit d8c213a2e5
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ChocolArm64/Instruction/AInstEmitSimdHash.cs Normal file
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using ChocolArm64.Decoder;
using ChocolArm64.Translation;
namespace ChocolArm64.Instruction
{
static partial class AInstEmit
{
#region "Sha256"
public static void Sha256h_V(AILEmitterCtx Context)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
Context.EmitLdvec(Op.Rd);
Context.EmitLdvec(Op.Rn);
Context.EmitLdvec(Op.Rm);
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.HashLower));
Context.EmitStvec(Op.Rd);
}
public static void Sha256h2_V(AILEmitterCtx Context)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
Context.EmitLdvec(Op.Rd);
Context.EmitLdvec(Op.Rn);
Context.EmitLdvec(Op.Rm);
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.HashUpper));
Context.EmitStvec(Op.Rd);
}
public static void Sha256su0_V(AILEmitterCtx Context)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
Context.EmitLdvec(Op.Rd);
Context.EmitLdvec(Op.Rn);
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.SchedulePart1));
Context.EmitStvec(Op.Rd);
}
public static void Sha256su1_V(AILEmitterCtx Context)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
Context.EmitLdvec(Op.Rd);
Context.EmitLdvec(Op.Rn);
Context.EmitLdvec(Op.Rm);
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.SchedulePart2));
Context.EmitStvec(Op.Rd);
}
#endregion
}
}