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Remove prefix from ChocolArm64 classes - Part 1

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This commit is contained in:
Alex Barney 2018-10-30 12:27:01 -05:00
commit ded51fdb07
161 changed files with 3500 additions and 3500 deletions
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ChocolArm64/AOpCodeTable.cs
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@ -1,713 +0,0 @@
using ChocolArm64.Decoder;
using ChocolArm64.Decoder32;
using ChocolArm64.Instruction;
using ChocolArm64.Instruction32;
using ChocolArm64.State;
using System;
using System.Collections.Generic;
namespace ChocolArm64
{
static class AOpCodeTable
{
static AOpCodeTable()
{
#region "OpCode Table (AArch32)"
//Integer
SetA32("<<<<1010xxxxxxxxxxxxxxxxxxxxxxxx", A32InstInterpret.B, typeof(A32OpCodeBImmAl));
SetA32("<<<<1011xxxxxxxxxxxxxxxxxxxxxxxx", A32InstInterpret.Bl, typeof(A32OpCodeBImmAl));
SetA32("1111101xxxxxxxxxxxxxxxxxxxxxxxxx", A32InstInterpret.Blx, typeof(A32OpCodeBImmAl));
#endregion
#region "OpCode Table (AArch64)"
//Integer
SetA64("x0011010000xxxxx000000xxxxxxxxxx", AInstEmit.Adc, typeof(AOpCodeAluRs));
SetA64("x0111010000xxxxx000000xxxxxxxxxx", AInstEmit.Adcs, typeof(AOpCodeAluRs));
SetA64("x00100010xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Add, typeof(AOpCodeAluImm));
SetA64("00001011<<0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Add, typeof(AOpCodeAluRs));
SetA64("10001011<<0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Add, typeof(AOpCodeAluRs));
SetA64("x0001011001xxxxxxxx0xxxxxxxxxxxx", AInstEmit.Add, typeof(AOpCodeAluRx));
SetA64("x0001011001xxxxxxxx100xxxxxxxxxx", AInstEmit.Add, typeof(AOpCodeAluRx));
SetA64("x01100010xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Adds, typeof(AOpCodeAluImm));
SetA64("00101011<<0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Adds, typeof(AOpCodeAluRs));
SetA64("10101011<<0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Adds, typeof(AOpCodeAluRs));
SetA64("x0101011001xxxxxxxx0xxxxxxxxxxxx", AInstEmit.Adds, typeof(AOpCodeAluRx));
SetA64("x0101011001xxxxxxxx100xxxxxxxxxx", AInstEmit.Adds, typeof(AOpCodeAluRx));
SetA64("0xx10000xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Adr, typeof(AOpCodeAdr));
SetA64("1xx10000xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Adrp, typeof(AOpCodeAdr));
SetA64("0001001000xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.And, typeof(AOpCodeAluImm));
SetA64("100100100xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.And, typeof(AOpCodeAluImm));
SetA64("00001010xx0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.And, typeof(AOpCodeAluRs));
SetA64("10001010xx0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.And, typeof(AOpCodeAluRs));
SetA64("0111001000xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ands, typeof(AOpCodeAluImm));
SetA64("111100100xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ands, typeof(AOpCodeAluImm));
SetA64("01101010xx0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Ands, typeof(AOpCodeAluRs));
SetA64("11101010xx0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ands, typeof(AOpCodeAluRs));
SetA64("x0011010110xxxxx001010xxxxxxxxxx", AInstEmit.Asrv, typeof(AOpCodeAluRs));
SetA64("000101xxxxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.B, typeof(AOpCodeBImmAl));
SetA64("01010100xxxxxxxxxxxxxxxxxxx0xxxx", AInstEmit.B_Cond, typeof(AOpCodeBImmCond));
SetA64("00110011000xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Bfm, typeof(AOpCodeBfm));
SetA64("1011001101xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Bfm, typeof(AOpCodeBfm));
SetA64("00001010xx1xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Bic, typeof(AOpCodeAluRs));
SetA64("10001010xx1xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Bic, typeof(AOpCodeAluRs));
SetA64("01101010xx1xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Bics, typeof(AOpCodeAluRs));
SetA64("11101010xx1xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Bics, typeof(AOpCodeAluRs));
SetA64("100101xxxxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Bl, typeof(AOpCodeBImmAl));
SetA64("1101011000111111000000xxxxx00000", AInstEmit.Blr, typeof(AOpCodeBReg));
SetA64("1101011000011111000000xxxxx00000", AInstEmit.Br, typeof(AOpCodeBReg));
SetA64("11010100001xxxxxxxxxxxxxxxx00000", AInstEmit.Brk, typeof(AOpCodeException));
SetA64("x0110101xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Cbnz, typeof(AOpCodeBImmCmp));
SetA64("x0110100xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Cbz, typeof(AOpCodeBImmCmp));
SetA64("x0111010010xxxxxxxxx10xxxxx0xxxx", AInstEmit.Ccmn, typeof(AOpCodeCcmpImm));
SetA64("x0111010010xxxxxxxxx00xxxxx0xxxx", AInstEmit.Ccmn, typeof(AOpCodeCcmpReg));
SetA64("x1111010010xxxxxxxxx10xxxxx0xxxx", AInstEmit.Ccmp, typeof(AOpCodeCcmpImm));
SetA64("x1111010010xxxxxxxxx00xxxxx0xxxx", AInstEmit.Ccmp, typeof(AOpCodeCcmpReg));
SetA64("11010101000000110011xxxx01011111", AInstEmit.Clrex, typeof(AOpCodeSystem));
SetA64("x101101011000000000101xxxxxxxxxx", AInstEmit.Cls, typeof(AOpCodeAlu));
SetA64("x101101011000000000100xxxxxxxxxx", AInstEmit.Clz, typeof(AOpCodeAlu));
SetA64("00011010110xxxxx010000xxxxxxxxxx", AInstEmit.Crc32b, typeof(AOpCodeAluRs));
SetA64("00011010110xxxxx010001xxxxxxxxxx", AInstEmit.Crc32h, typeof(AOpCodeAluRs));
SetA64("00011010110xxxxx010010xxxxxxxxxx", AInstEmit.Crc32w, typeof(AOpCodeAluRs));
SetA64("10011010110xxxxx010011xxxxxxxxxx", AInstEmit.Crc32x, typeof(AOpCodeAluRs));
SetA64("00011010110xxxxx010100xxxxxxxxxx", AInstEmit.Crc32cb, typeof(AOpCodeAluRs));
SetA64("00011010110xxxxx010101xxxxxxxxxx", AInstEmit.Crc32ch, typeof(AOpCodeAluRs));
SetA64("00011010110xxxxx010110xxxxxxxxxx", AInstEmit.Crc32cw, typeof(AOpCodeAluRs));
SetA64("10011010110xxxxx010111xxxxxxxxxx", AInstEmit.Crc32cx, typeof(AOpCodeAluRs));
SetA64("x0011010100xxxxxxxxx00xxxxxxxxxx", AInstEmit.Csel, typeof(AOpCodeCsel));
SetA64("x0011010100xxxxxxxxx01xxxxxxxxxx", AInstEmit.Csinc, typeof(AOpCodeCsel));
SetA64("x1011010100xxxxxxxxx00xxxxxxxxxx", AInstEmit.Csinv, typeof(AOpCodeCsel));
SetA64("x1011010100xxxxxxxxx01xxxxxxxxxx", AInstEmit.Csneg, typeof(AOpCodeCsel));
SetA64("11010101000000110011xxxx10111111", AInstEmit.Dmb, typeof(AOpCodeSystem));
SetA64("11010101000000110011xxxx10011111", AInstEmit.Dsb, typeof(AOpCodeSystem));
SetA64("01001010xx1xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Eon, typeof(AOpCodeAluRs));
SetA64("11001010xx1xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Eon, typeof(AOpCodeAluRs));
SetA64("0101001000xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Eor, typeof(AOpCodeAluImm));
SetA64("110100100xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Eor, typeof(AOpCodeAluImm));
SetA64("01001010xx0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Eor, typeof(AOpCodeAluRs));
SetA64("11001010xx0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Eor, typeof(AOpCodeAluRs));
SetA64("00010011100xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Extr, typeof(AOpCodeAluRs));
SetA64("10010011110xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Extr, typeof(AOpCodeAluRs));
SetA64("11010101000000110010xxxxxxx11111", AInstEmit.Hint, typeof(AOpCodeSystem));
SetA64("11010101000000110011xxxx11011111", AInstEmit.Isb, typeof(AOpCodeSystem));
SetA64("xx001000110xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Ldar, typeof(AOpCodeMemEx));
SetA64("1x001000011xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Ldaxp, typeof(AOpCodeMemEx));
SetA64("xx001000010xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Ldaxr, typeof(AOpCodeMemEx));
SetA64("<<10100xx1xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldp, typeof(AOpCodeMemPair));
SetA64("xx111000010xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeMemImm));
SetA64("xx11100101xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeMemImm));
SetA64("xx111000011xxxxxxxxx10xxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeMemReg));
SetA64("xx011000xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.LdrLit, typeof(AOpCodeMemLit));
SetA64("0x1110001x0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldrs, typeof(AOpCodeMemImm));
SetA64("0x1110011xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldrs, typeof(AOpCodeMemImm));
SetA64("10111000100xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldrs, typeof(AOpCodeMemImm));
SetA64("1011100110xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldrs, typeof(AOpCodeMemImm));
SetA64("0x1110001x1xxxxxxxxx10xxxxxxxxxx", AInstEmit.Ldrs, typeof(AOpCodeMemReg));
SetA64("10111000101xxxxxxxxx10xxxxxxxxxx", AInstEmit.Ldrs, typeof(AOpCodeMemReg));
SetA64("xx001000010xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Ldxr, typeof(AOpCodeMemEx));
SetA64("1x001000011xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Ldxp, typeof(AOpCodeMemEx));
SetA64("x0011010110xxxxx001000xxxxxxxxxx", AInstEmit.Lslv, typeof(AOpCodeAluRs));
SetA64("x0011010110xxxxx001001xxxxxxxxxx", AInstEmit.Lsrv, typeof(AOpCodeAluRs));
SetA64("x0011011000xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Madd, typeof(AOpCodeMul));
SetA64("0111001010xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Movk, typeof(AOpCodeMov));
SetA64("111100101xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Movk, typeof(AOpCodeMov));
SetA64("0001001010xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Movn, typeof(AOpCodeMov));
SetA64("100100101xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Movn, typeof(AOpCodeMov));
SetA64("0101001010xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Movz, typeof(AOpCodeMov));
SetA64("110100101xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Movz, typeof(AOpCodeMov));
SetA64("110101010011xxxxxxxxxxxxxxxxxxxx", AInstEmit.Mrs, typeof(AOpCodeSystem));
SetA64("110101010001xxxxxxxxxxxxxxxxxxxx", AInstEmit.Msr, typeof(AOpCodeSystem));
SetA64("x0011011000xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Msub, typeof(AOpCodeMul));
SetA64("11010101000000110010000000011111", AInstEmit.Nop, typeof(AOpCodeSystem));
SetA64("00101010xx1xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Orn, typeof(AOpCodeAluRs));
SetA64("10101010xx1xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Orn, typeof(AOpCodeAluRs));
SetA64("0011001000xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Orr, typeof(AOpCodeAluImm));
SetA64("101100100xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Orr, typeof(AOpCodeAluImm));
SetA64("00101010xx0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Orr, typeof(AOpCodeAluRs));
SetA64("10101010xx0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Orr, typeof(AOpCodeAluRs));
SetA64("1111100110xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Pfrm, typeof(AOpCodeMemImm));
SetA64("11111000100xxxxxxxxx00xxxxxxxxxx", AInstEmit.Pfrm, typeof(AOpCodeMemImm));
SetA64("11011000xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Pfrm, typeof(AOpCodeMemLit));
SetA64("x101101011000000000000xxxxxxxxxx", AInstEmit.Rbit, typeof(AOpCodeAlu));
SetA64("1101011001011111000000xxxxx00000", AInstEmit.Ret, typeof(AOpCodeBReg));
SetA64("x101101011000000000001xxxxxxxxxx", AInstEmit.Rev16, typeof(AOpCodeAlu));
SetA64("x101101011000000000010xxxxxxxxxx", AInstEmit.Rev32, typeof(AOpCodeAlu));
SetA64("1101101011000000000011xxxxxxxxxx", AInstEmit.Rev64, typeof(AOpCodeAlu));
SetA64("x0011010110xxxxx001011xxxxxxxxxx", AInstEmit.Rorv, typeof(AOpCodeAluRs));
SetA64("x1011010000xxxxx000000xxxxxxxxxx", AInstEmit.Sbc, typeof(AOpCodeAluRs));
SetA64("x1111010000xxxxx000000xxxxxxxxxx", AInstEmit.Sbcs, typeof(AOpCodeAluRs));
SetA64("00010011000xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Sbfm, typeof(AOpCodeBfm));
SetA64("1001001101xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Sbfm, typeof(AOpCodeBfm));
SetA64("x0011010110xxxxx000011xxxxxxxxxx", AInstEmit.Sdiv, typeof(AOpCodeAluRs));
SetA64("10011011001xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Smaddl, typeof(AOpCodeMul));
SetA64("10011011001xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Smsubl, typeof(AOpCodeMul));
SetA64("10011011010xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Smulh, typeof(AOpCodeMul));
SetA64("xx001000100xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Stlr, typeof(AOpCodeMemEx));
SetA64("1x001000001xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Stlxp, typeof(AOpCodeMemEx));
SetA64("xx001000000xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Stlxr, typeof(AOpCodeMemEx));
SetA64("x010100xx0xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Stp, typeof(AOpCodeMemPair));
SetA64("xx111000000xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeMemImm));
SetA64("xx11100100xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeMemImm));
SetA64("xx111000001xxxxxxxxx10xxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeMemReg));
SetA64("1x001000001xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Stxp, typeof(AOpCodeMemEx));
SetA64("xx001000000xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Stxr, typeof(AOpCodeMemEx));
SetA64("x10100010xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Sub, typeof(AOpCodeAluImm));
SetA64("01001011<<0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Sub, typeof(AOpCodeAluRs));
SetA64("11001011<<0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Sub, typeof(AOpCodeAluRs));
SetA64("x1001011001xxxxxxxx0xxxxxxxxxxxx", AInstEmit.Sub, typeof(AOpCodeAluRx));
SetA64("x1001011001xxxxxxxx100xxxxxxxxxx", AInstEmit.Sub, typeof(AOpCodeAluRx));
SetA64("x11100010xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Subs, typeof(AOpCodeAluImm));
SetA64("01101011<<0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Subs, typeof(AOpCodeAluRs));
SetA64("11101011<<0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Subs, typeof(AOpCodeAluRs));
SetA64("x1101011001xxxxxxxx0xxxxxxxxxxxx", AInstEmit.Subs, typeof(AOpCodeAluRx));
SetA64("x1101011001xxxxxxxx100xxxxxxxxxx", AInstEmit.Subs, typeof(AOpCodeAluRx));
SetA64("11010100000xxxxxxxxxxxxxxxx00001", AInstEmit.Svc, typeof(AOpCodeException));
SetA64("1101010100001xxxxxxxxxxxxxxxxxxx", AInstEmit.Sys, typeof(AOpCodeSystem));
SetA64("x0110111xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Tbnz, typeof(AOpCodeBImmTest));
SetA64("x0110110xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Tbz, typeof(AOpCodeBImmTest));
SetA64("01010011000xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Ubfm, typeof(AOpCodeBfm));
SetA64("1101001101xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ubfm, typeof(AOpCodeBfm));
SetA64("x0011010110xxxxx000010xxxxxxxxxx", AInstEmit.Udiv, typeof(AOpCodeAluRs));
SetA64("10011011101xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Umaddl, typeof(AOpCodeMul));
SetA64("10011011101xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Umsubl, typeof(AOpCodeMul));
SetA64("10011011110xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Umulh, typeof(AOpCodeMul));
//Vector
SetA64("0101111011100000101110xxxxxxxxxx", AInstEmit.Abs_S, typeof(AOpCodeSimd));
SetA64("0>001110<<100000101110xxxxxxxxxx", AInstEmit.Abs_V, typeof(AOpCodeSimd));
SetA64("01011110111xxxxx100001xxxxxxxxxx", AInstEmit.Add_S, typeof(AOpCodeSimdReg));
SetA64("0>001110<<1xxxxx100001xxxxxxxxxx", AInstEmit.Add_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx010000xxxxxxxxxx", AInstEmit.Addhn_V, typeof(AOpCodeSimdReg));
SetA64("0101111011110001101110xxxxxxxxxx", AInstEmit.Addp_S, typeof(AOpCodeSimd));
SetA64("0>001110<<1xxxxx101111xxxxxxxxxx", AInstEmit.Addp_V, typeof(AOpCodeSimdReg));
SetA64("000011100x110001101110xxxxxxxxxx", AInstEmit.Addv_V, typeof(AOpCodeSimd));
SetA64("01001110<<110001101110xxxxxxxxxx", AInstEmit.Addv_V, typeof(AOpCodeSimd));
SetA64("0100111000101000010110xxxxxxxxxx", AInstEmit.Aesd_V, typeof(AOpCodeSimd));
SetA64("0100111000101000010010xxxxxxxxxx", AInstEmit.Aese_V, typeof(AOpCodeSimd));
SetA64("0100111000101000011110xxxxxxxxxx", AInstEmit.Aesimc_V, typeof(AOpCodeSimd));
SetA64("0100111000101000011010xxxxxxxxxx", AInstEmit.Aesmc_V, typeof(AOpCodeSimd));
SetA64("0x001110001xxxxx000111xxxxxxxxxx", AInstEmit.And_V, typeof(AOpCodeSimdReg));
SetA64("0x001110011xxxxx000111xxxxxxxxxx", AInstEmit.Bic_V, typeof(AOpCodeSimdReg));
SetA64("0x10111100000xxx<<x101xxxxxxxxxx", AInstEmit.Bic_Vi, typeof(AOpCodeSimdImm));
SetA64("0x101110111xxxxx000111xxxxxxxxxx", AInstEmit.Bif_V, typeof(AOpCodeSimdReg));
SetA64("0x101110101xxxxx000111xxxxxxxxxx", AInstEmit.Bit_V, typeof(AOpCodeSimdReg));
SetA64("0x101110011xxxxx000111xxxxxxxxxx", AInstEmit.Bsl_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<100000010010xxxxxxxxxx", AInstEmit.Cls_V, typeof(AOpCodeSimd));
SetA64("0x101110<<100000010010xxxxxxxxxx", AInstEmit.Clz_V, typeof(AOpCodeSimd));
SetA64("01111110111xxxxx100011xxxxxxxxxx", AInstEmit.Cmeq_S, typeof(AOpCodeSimdReg));
SetA64("0101111011100000100110xxxxxxxxxx", AInstEmit.Cmeq_S, typeof(AOpCodeSimd));
SetA64("0>101110<<1xxxxx100011xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimdReg));
SetA64("0>001110<<100000100110xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimd));
SetA64("01011110111xxxxx001111xxxxxxxxxx", AInstEmit.Cmge_S, typeof(AOpCodeSimdReg));
SetA64("0111111011100000100010xxxxxxxxxx", AInstEmit.Cmge_S, typeof(AOpCodeSimd));
SetA64("0>001110<<1xxxxx001111xxxxxxxxxx", AInstEmit.Cmge_V, typeof(AOpCodeSimdReg));
SetA64("0>101110<<100000100010xxxxxxxxxx", AInstEmit.Cmge_V, typeof(AOpCodeSimd));
SetA64("01011110111xxxxx001101xxxxxxxxxx", AInstEmit.Cmgt_S, typeof(AOpCodeSimdReg));
SetA64("0101111011100000100010xxxxxxxxxx", AInstEmit.Cmgt_S, typeof(AOpCodeSimd));
SetA64("0>001110<<1xxxxx001101xxxxxxxxxx", AInstEmit.Cmgt_V, typeof(AOpCodeSimdReg));
SetA64("0>001110<<100000100010xxxxxxxxxx", AInstEmit.Cmgt_V, typeof(AOpCodeSimd));
SetA64("01111110111xxxxx001101xxxxxxxxxx", AInstEmit.Cmhi_S, typeof(AOpCodeSimdReg));
SetA64("0>101110<<1xxxxx001101xxxxxxxxxx", AInstEmit.Cmhi_V, typeof(AOpCodeSimdReg));
SetA64("01111110111xxxxx001111xxxxxxxxxx", AInstEmit.Cmhs_S, typeof(AOpCodeSimdReg));
SetA64("0>101110<<1xxxxx001111xxxxxxxxxx", AInstEmit.Cmhs_V, typeof(AOpCodeSimdReg));
SetA64("0111111011100000100110xxxxxxxxxx", AInstEmit.Cmle_S, typeof(AOpCodeSimd));
SetA64("0>101110<<100000100110xxxxxxxxxx", AInstEmit.Cmle_V, typeof(AOpCodeSimd));
SetA64("0101111011100000101010xxxxxxxxxx", AInstEmit.Cmlt_S, typeof(AOpCodeSimd));
SetA64("0>001110<<100000101010xxxxxxxxxx", AInstEmit.Cmlt_V, typeof(AOpCodeSimd));
SetA64("01011110111xxxxx100011xxxxxxxxxx", AInstEmit.Cmtst_S, typeof(AOpCodeSimdReg));
SetA64("0>001110<<1xxxxx100011xxxxxxxxxx", AInstEmit.Cmtst_V, typeof(AOpCodeSimdReg));
SetA64("0x00111000100000010110xxxxxxxxxx", AInstEmit.Cnt_V, typeof(AOpCodeSimd));
SetA64("0x001110000xxxxx000011xxxxxxxxxx", AInstEmit.Dup_Gp, typeof(AOpCodeSimdIns));
SetA64("01011110000xxxxx000001xxxxxxxxxx", AInstEmit.Dup_S, typeof(AOpCodeSimdIns));
SetA64("0x001110000xxxxx000001xxxxxxxxxx", AInstEmit.Dup_V, typeof(AOpCodeSimdIns));
SetA64("0x101110001xxxxx000111xxxxxxxxxx", AInstEmit.Eor_V, typeof(AOpCodeSimdReg));
SetA64("0>101110000xxxxx0<xxx0xxxxxxxxxx", AInstEmit.Ext_V, typeof(AOpCodeSimdExt));
SetA64("011111101x1xxxxx110101xxxxxxxxxx", AInstEmit.Fabd_S, typeof(AOpCodeSimdReg));
SetA64("000111100x100000110000xxxxxxxxxx", AInstEmit.Fabs_S, typeof(AOpCodeSimd));
SetA64("0>0011101<100000111110xxxxxxxxxx", AInstEmit.Fabs_V, typeof(AOpCodeSimd));
SetA64("000111100x1xxxxx001010xxxxxxxxxx", AInstEmit.Fadd_S, typeof(AOpCodeSimdReg));
SetA64("0>0011100<1xxxxx110101xxxxxxxxxx", AInstEmit.Fadd_V, typeof(AOpCodeSimdReg));
SetA64("011111100x110000110110xxxxxxxxxx", AInstEmit.Faddp_S, typeof(AOpCodeSimd));
SetA64("0>1011100<1xxxxx110101xxxxxxxxxx", AInstEmit.Faddp_V, typeof(AOpCodeSimdReg));
SetA64("000111100x1xxxxxxxxx01xxxxx0xxxx", AInstEmit.Fccmp_S, typeof(AOpCodeSimdFcond));
SetA64("000111100x1xxxxxxxxx01xxxxx1xxxx", AInstEmit.Fccmpe_S, typeof(AOpCodeSimdFcond));
SetA64("010111100x1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmeq_S, typeof(AOpCodeSimdReg));
SetA64("010111101x100000110110xxxxxxxxxx", AInstEmit.Fcmeq_S, typeof(AOpCodeSimd));
SetA64("0>0011100<1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmeq_V, typeof(AOpCodeSimdReg));
SetA64("0>0011101<100000110110xxxxxxxxxx", AInstEmit.Fcmeq_V, typeof(AOpCodeSimd));
SetA64("011111100x1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmge_S, typeof(AOpCodeSimdReg));
SetA64("011111101x100000110010xxxxxxxxxx", AInstEmit.Fcmge_S, typeof(AOpCodeSimd));
SetA64("0>1011100<1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmge_V, typeof(AOpCodeSimdReg));
SetA64("0>1011101<100000110010xxxxxxxxxx", AInstEmit.Fcmge_V, typeof(AOpCodeSimd));
SetA64("011111101x1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmgt_S, typeof(AOpCodeSimdReg));
SetA64("010111101x100000110010xxxxxxxxxx", AInstEmit.Fcmgt_S, typeof(AOpCodeSimd));
SetA64("0>1011101<1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmgt_V, typeof(AOpCodeSimdReg));
SetA64("0>0011101<100000110010xxxxxxxxxx", AInstEmit.Fcmgt_V, typeof(AOpCodeSimd));
SetA64("011111101x100000110110xxxxxxxxxx", AInstEmit.Fcmle_S, typeof(AOpCodeSimd));
SetA64("0>1011101<100000110110xxxxxxxxxx", AInstEmit.Fcmle_V, typeof(AOpCodeSimd));
SetA64("010111101x100000111010xxxxxxxxxx", AInstEmit.Fcmlt_S, typeof(AOpCodeSimd));
SetA64("0>0011101<100000111010xxxxxxxxxx", AInstEmit.Fcmlt_V, typeof(AOpCodeSimd));
SetA64("000111100x1xxxxx001000xxxxx0x000", AInstEmit.Fcmp_S, typeof(AOpCodeSimdReg));
SetA64("000111100x1xxxxx001000xxxxx1x000", AInstEmit.Fcmpe_S, typeof(AOpCodeSimdReg));
SetA64("000111100x1xxxxxxxxx11xxxxxxxxxx", AInstEmit.Fcsel_S, typeof(AOpCodeSimdFcond));
SetA64("000111100x10001xx10000xxxxxxxxxx", AInstEmit.Fcvt_S, typeof(AOpCodeSimd));
SetA64("x00111100x100100000000xxxxxxxxxx", AInstEmit.Fcvtas_Gp, typeof(AOpCodeSimdCvt));
SetA64("x00111100x100101000000xxxxxxxxxx", AInstEmit.Fcvtau_Gp, typeof(AOpCodeSimdCvt));
SetA64("0x0011100x100001011110xxxxxxxxxx", AInstEmit.Fcvtl_V, typeof(AOpCodeSimd));
SetA64("x00111100x110000000000xxxxxxxxxx", AInstEmit.Fcvtms_Gp, typeof(AOpCodeSimdCvt));
SetA64("x00111100x110001000000xxxxxxxxxx", AInstEmit.Fcvtmu_Gp, typeof(AOpCodeSimdCvt));
SetA64("0x0011100x100001011010xxxxxxxxxx", AInstEmit.Fcvtn_V, typeof(AOpCodeSimd));
SetA64("010111100x100001101010xxxxxxxxxx", AInstEmit.Fcvtns_S, typeof(AOpCodeSimd));
SetA64("0>0011100<100001101010xxxxxxxxxx", AInstEmit.Fcvtns_V, typeof(AOpCodeSimd));
SetA64("011111100x100001101010xxxxxxxxxx", AInstEmit.Fcvtnu_S, typeof(AOpCodeSimd));
SetA64("0>1011100<100001101010xxxxxxxxxx", AInstEmit.Fcvtnu_V, typeof(AOpCodeSimd));
SetA64("x00111100x101000000000xxxxxxxxxx", AInstEmit.Fcvtps_Gp, typeof(AOpCodeSimdCvt));
SetA64("x00111100x101001000000xxxxxxxxxx", AInstEmit.Fcvtpu_Gp, typeof(AOpCodeSimdCvt));
SetA64("x00111100x111000000000xxxxxxxxxx", AInstEmit.Fcvtzs_Gp, typeof(AOpCodeSimdCvt));
SetA64("x00111100x011000xxxxxxxxxxxxxxxx", AInstEmit.Fcvtzs_Gp_Fix, typeof(AOpCodeSimdCvt));
SetA64("010111101x100001101110xxxxxxxxxx", AInstEmit.Fcvtzs_S, typeof(AOpCodeSimd));
SetA64("0>0011101<100001101110xxxxxxxxxx", AInstEmit.Fcvtzs_V, typeof(AOpCodeSimd));
SetA64("0x0011110>>xxxxx111111xxxxxxxxxx", AInstEmit.Fcvtzs_V, typeof(AOpCodeSimdShImm));
SetA64("x00111100x111001000000xxxxxxxxxx", AInstEmit.Fcvtzu_Gp, typeof(AOpCodeSimdCvt));
SetA64("x00111100x011001xxxxxxxxxxxxxxxx", AInstEmit.Fcvtzu_Gp_Fix, typeof(AOpCodeSimdCvt));
SetA64("011111101x100001101110xxxxxxxxxx", AInstEmit.Fcvtzu_S, typeof(AOpCodeSimd));
SetA64("0>1011101<100001101110xxxxxxxxxx", AInstEmit.Fcvtzu_V, typeof(AOpCodeSimd));
SetA64("0x1011110>>xxxxx111111xxxxxxxxxx", AInstEmit.Fcvtzu_V, typeof(AOpCodeSimdShImm));
SetA64("000111100x1xxxxx000110xxxxxxxxxx", AInstEmit.Fdiv_S, typeof(AOpCodeSimdReg));
SetA64("0>1011100<1xxxxx111111xxxxxxxxxx", AInstEmit.Fdiv_V, typeof(AOpCodeSimdReg));
SetA64("000111110x0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Fmadd_S, typeof(AOpCodeSimdReg));
SetA64("000111100x1xxxxx010010xxxxxxxxxx", AInstEmit.Fmax_S, typeof(AOpCodeSimdReg));
SetA64("0>0011100<1xxxxx111101xxxxxxxxxx", AInstEmit.Fmax_V, typeof(AOpCodeSimdReg));
SetA64("000111100x1xxxxx011010xxxxxxxxxx", AInstEmit.Fmaxnm_S, typeof(AOpCodeSimdReg));
SetA64("0>0011100<1xxxxx110001xxxxxxxxxx", AInstEmit.Fmaxnm_V, typeof(AOpCodeSimdReg));
SetA64("0>1011100<1xxxxx111101xxxxxxxxxx", AInstEmit.Fmaxp_V, typeof(AOpCodeSimdReg));
SetA64("000111100x1xxxxx010110xxxxxxxxxx", AInstEmit.Fmin_S, typeof(AOpCodeSimdReg));
SetA64("0>0011101<1xxxxx111101xxxxxxxxxx", AInstEmit.Fmin_V, typeof(AOpCodeSimdReg));
SetA64("000111100x1xxxxx011110xxxxxxxxxx", AInstEmit.Fminnm_S, typeof(AOpCodeSimdReg));
SetA64("0>0011101<1xxxxx110001xxxxxxxxxx", AInstEmit.Fminnm_V, typeof(AOpCodeSimdReg));
SetA64("0>1011101<1xxxxx111101xxxxxxxxxx", AInstEmit.Fminp_V, typeof(AOpCodeSimdReg));
SetA64("010111111xxxxxxx0001x0xxxxxxxxxx", AInstEmit.Fmla_Se, typeof(AOpCodeSimdRegElemF));
SetA64("0>0011100<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmla_V, typeof(AOpCodeSimdReg));
SetA64("0>0011111<xxxxxx0001x0xxxxxxxxxx", AInstEmit.Fmla_Ve, typeof(AOpCodeSimdRegElemF));
SetA64("010111111xxxxxxx0101x0xxxxxxxxxx", AInstEmit.Fmls_Se, typeof(AOpCodeSimdRegElemF));
SetA64("0>0011101<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmls_V, typeof(AOpCodeSimdReg));
SetA64("0>0011111<xxxxxx0101x0xxxxxxxxxx", AInstEmit.Fmls_Ve, typeof(AOpCodeSimdRegElemF));
SetA64("000111100x100000010000xxxxxxxxxx", AInstEmit.Fmov_S, typeof(AOpCodeSimd));
SetA64("00011110xx1xxxxxxxx100xxxxxxxxxx", AInstEmit.Fmov_Si, typeof(AOpCodeSimdFmov));
SetA64("0xx0111100000xxx111101xxxxxxxxxx", AInstEmit.Fmov_V, typeof(AOpCodeSimdImm));
SetA64("x00111100x100110000000xxxxxxxxxx", AInstEmit.Fmov_Ftoi, typeof(AOpCodeSimdCvt));
SetA64("x00111100x100111000000xxxxxxxxxx", AInstEmit.Fmov_Itof, typeof(AOpCodeSimdCvt));
SetA64("1001111010101110000000xxxxxxxxxx", AInstEmit.Fmov_Ftoi1, typeof(AOpCodeSimdCvt));
SetA64("1001111010101111000000xxxxxxxxxx", AInstEmit.Fmov_Itof1, typeof(AOpCodeSimdCvt));
SetA64("000111110x0xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Fmsub_S, typeof(AOpCodeSimdReg));
SetA64("000111100x1xxxxx000010xxxxxxxxxx", AInstEmit.Fmul_S, typeof(AOpCodeSimdReg));
SetA64("010111111xxxxxxx1001x0xxxxxxxxxx", AInstEmit.Fmul_Se, typeof(AOpCodeSimdRegElemF));
SetA64("0>1011100<1xxxxx110111xxxxxxxxxx", AInstEmit.Fmul_V, typeof(AOpCodeSimdReg));
SetA64("0>0011111<xxxxxx1001x0xxxxxxxxxx", AInstEmit.Fmul_Ve, typeof(AOpCodeSimdRegElemF));
SetA64("010111100x1xxxxx110111xxxxxxxxxx", AInstEmit.Fmulx_S, typeof(AOpCodeSimdReg));
SetA64("011111111xxxxxxx1001x0xxxxxxxxxx", AInstEmit.Fmulx_Se, typeof(AOpCodeSimdRegElemF));
SetA64("0>0011100<1xxxxx110111xxxxxxxxxx", AInstEmit.Fmulx_V, typeof(AOpCodeSimdReg));
SetA64("0>1011111<xxxxxx1001x0xxxxxxxxxx", AInstEmit.Fmulx_Ve, typeof(AOpCodeSimdRegElemF));
SetA64("000111100x100001010000xxxxxxxxxx", AInstEmit.Fneg_S, typeof(AOpCodeSimd));
SetA64("0>1011101<100000111110xxxxxxxxxx", AInstEmit.Fneg_V, typeof(AOpCodeSimd));
SetA64("000111110x1xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Fnmadd_S, typeof(AOpCodeSimdReg));
SetA64("000111110x1xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Fnmsub_S, typeof(AOpCodeSimdReg));
SetA64("000111100x1xxxxx100010xxxxxxxxxx", AInstEmit.Fnmul_S, typeof(AOpCodeSimdReg));
SetA64("010111101x100001110110xxxxxxxxxx", AInstEmit.Frecpe_S, typeof(AOpCodeSimd));
SetA64("0>0011101<100001110110xxxxxxxxxx", AInstEmit.Frecpe_V, typeof(AOpCodeSimd));
SetA64("010111100x1xxxxx111111xxxxxxxxxx", AInstEmit.Frecps_S, typeof(AOpCodeSimdReg));
SetA64("0>0011100<1xxxxx111111xxxxxxxxxx", AInstEmit.Frecps_V, typeof(AOpCodeSimdReg));
SetA64("010111101x100001111110xxxxxxxxxx", AInstEmit.Frecpx_S, typeof(AOpCodeSimd));
SetA64("000111100x100110010000xxxxxxxxxx", AInstEmit.Frinta_S, typeof(AOpCodeSimd));
SetA64("0>1011100<100001100010xxxxxxxxxx", AInstEmit.Frinta_V, typeof(AOpCodeSimd));
SetA64("000111100x100111110000xxxxxxxxxx", AInstEmit.Frinti_S, typeof(AOpCodeSimd));
SetA64("0>1011101<100001100110xxxxxxxxxx", AInstEmit.Frinti_V, typeof(AOpCodeSimd));
SetA64("000111100x100101010000xxxxxxxxxx", AInstEmit.Frintm_S, typeof(AOpCodeSimd));
SetA64("0>0011100<100001100110xxxxxxxxxx", AInstEmit.Frintm_V, typeof(AOpCodeSimd));
SetA64("000111100x100100010000xxxxxxxxxx", AInstEmit.Frintn_S, typeof(AOpCodeSimd));
SetA64("0>0011100<100001100010xxxxxxxxxx", AInstEmit.Frintn_V, typeof(AOpCodeSimd));
SetA64("000111100x100100110000xxxxxxxxxx", AInstEmit.Frintp_S, typeof(AOpCodeSimd));
SetA64("0>0011101<100001100010xxxxxxxxxx", AInstEmit.Frintp_V, typeof(AOpCodeSimd));
SetA64("000111100x100111010000xxxxxxxxxx", AInstEmit.Frintx_S, typeof(AOpCodeSimd));
SetA64("0>1011100<100001100110xxxxxxxxxx", AInstEmit.Frintx_V, typeof(AOpCodeSimd));
SetA64("011111101x100001110110xxxxxxxxxx", AInstEmit.Frsqrte_S, typeof(AOpCodeSimd));
SetA64("0>1011101<100001110110xxxxxxxxxx", AInstEmit.Frsqrte_V, typeof(AOpCodeSimd));
SetA64("010111101x1xxxxx111111xxxxxxxxxx", AInstEmit.Frsqrts_S, typeof(AOpCodeSimdReg));
SetA64("0>0011101<1xxxxx111111xxxxxxxxxx", AInstEmit.Frsqrts_V, typeof(AOpCodeSimdReg));
SetA64("000111100x100001110000xxxxxxxxxx", AInstEmit.Fsqrt_S, typeof(AOpCodeSimd));
SetA64("0>1011101<100001111110xxxxxxxxxx", AInstEmit.Fsqrt_V, typeof(AOpCodeSimd));
SetA64("000111100x1xxxxx001110xxxxxxxxxx", AInstEmit.Fsub_S, typeof(AOpCodeSimdReg));
SetA64("0>0011101<1xxxxx110101xxxxxxxxxx", AInstEmit.Fsub_V, typeof(AOpCodeSimdReg));
SetA64("01001110000xxxxx000111xxxxxxxxxx", AInstEmit.Ins_Gp, typeof(AOpCodeSimdIns));
SetA64("01101110000xxxxx0xxxx1xxxxxxxxxx", AInstEmit.Ins_V, typeof(AOpCodeSimdIns));
SetA64("0x00110001000000xxxxxxxxxxxxxxxx", AInstEmit.Ld__Vms, typeof(AOpCodeSimdMemMs));
SetA64("0x001100110xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ld__Vms, typeof(AOpCodeSimdMemMs));
SetA64("0x00110101x00000xxxxxxxxxxxxxxxx", AInstEmit.Ld__Vss, typeof(AOpCodeSimdMemSs));
SetA64("0x00110111xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ld__Vss, typeof(AOpCodeSimdMemSs));
SetA64("xx10110xx1xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldp, typeof(AOpCodeSimdMemPair));
SetA64("xx111100x10xxxxxxxxx00xxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeSimdMemImm));
SetA64("xx111100x10xxxxxxxxx01xxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeSimdMemImm));
SetA64("xx111100x10xxxxxxxxx11xxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeSimdMemImm));
SetA64("xx111101x1xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeSimdMemImm));
SetA64("xx111100x11xxxxxxxxx10xxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeSimdMemReg));
SetA64("xx011100xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.LdrLit, typeof(AOpCodeSimdMemLit));
SetA64("0x001110<<1xxxxx100101xxxxxxxxxx", AInstEmit.Mla_V, typeof(AOpCodeSimdReg));
SetA64("0x101111xxxxxxxx0000x0xxxxxxxxxx", AInstEmit.Mla_Ve, typeof(AOpCodeSimdRegElem));
SetA64("0x101110<<1xxxxx100101xxxxxxxxxx", AInstEmit.Mls_V, typeof(AOpCodeSimdReg));
SetA64("0x101111xxxxxxxx0100x0xxxxxxxxxx", AInstEmit.Mls_Ve, typeof(AOpCodeSimdRegElem));
SetA64("0x00111100000xxx0xx001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm));
SetA64("0x00111100000xxx10x001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm));
SetA64("0x00111100000xxx110x01xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm));
SetA64("0xx0111100000xxx111001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm));
SetA64("0x001110<<1xxxxx100111xxxxxxxxxx", AInstEmit.Mul_V, typeof(AOpCodeSimdReg));
SetA64("0x001111xxxxxxxx1000x0xxxxxxxxxx", AInstEmit.Mul_Ve, typeof(AOpCodeSimdRegElem));
SetA64("0x10111100000xxx0xx001xxxxxxxxxx", AInstEmit.Mvni_V, typeof(AOpCodeSimdImm));
SetA64("0x10111100000xxx10x001xxxxxxxxxx", AInstEmit.Mvni_V, typeof(AOpCodeSimdImm));
SetA64("0x10111100000xxx110x01xxxxxxxxxx", AInstEmit.Mvni_V, typeof(AOpCodeSimdImm));
SetA64("0111111011100000101110xxxxxxxxxx", AInstEmit.Neg_S, typeof(AOpCodeSimd));
SetA64("0>101110<<100000101110xxxxxxxxxx", AInstEmit.Neg_V, typeof(AOpCodeSimd));
SetA64("0x10111000100000010110xxxxxxxxxx", AInstEmit.Not_V, typeof(AOpCodeSimd));
SetA64("0x001110111xxxxx000111xxxxxxxxxx", AInstEmit.Orn_V, typeof(AOpCodeSimdReg));
SetA64("0x001110101xxxxx000111xxxxxxxxxx", AInstEmit.Orr_V, typeof(AOpCodeSimdReg));
SetA64("0x00111100000xxx<<x101xxxxxxxxxx", AInstEmit.Orr_Vi, typeof(AOpCodeSimdImm));
SetA64("0x101110<<1xxxxx010000xxxxxxxxxx", AInstEmit.Raddhn_V, typeof(AOpCodeSimdReg));
SetA64("0x10111001100000010110xxxxxxxxxx", AInstEmit.Rbit_V, typeof(AOpCodeSimd));
SetA64("0x00111000100000000110xxxxxxxxxx", AInstEmit.Rev16_V, typeof(AOpCodeSimd));
SetA64("0x1011100x100000000010xxxxxxxxxx", AInstEmit.Rev32_V, typeof(AOpCodeSimd));
SetA64("0x001110<<100000000010xxxxxxxxxx", AInstEmit.Rev64_V, typeof(AOpCodeSimd));
SetA64("0x00111100>>>xxx100011xxxxxxxxxx", AInstEmit.Rshrn_V, typeof(AOpCodeSimdShImm));
SetA64("0x101110<<1xxxxx011000xxxxxxxxxx", AInstEmit.Rsubhn_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx011111xxxxxxxxxx", AInstEmit.Saba_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx010100xxxxxxxxxx", AInstEmit.Sabal_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx011101xxxxxxxxxx", AInstEmit.Sabd_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Sabdl_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<100000011010xxxxxxxxxx", AInstEmit.Sadalp_V, typeof(AOpCodeSimd));
SetA64("0x001110<<1xxxxx000000xxxxxxxxxx", AInstEmit.Saddl_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<100000001010xxxxxxxxxx", AInstEmit.Saddlp_V, typeof(AOpCodeSimd));
SetA64("0x001110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Saddw_V, typeof(AOpCodeSimdReg));
SetA64("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp, typeof(AOpCodeSimdCvt));
SetA64("010111100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_S, typeof(AOpCodeSimd));
SetA64("0x0011100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_V, typeof(AOpCodeSimd));
SetA64("01011110000xxxxx000000xxxxxxxxxx", AInstEmit.Sha1c_V, typeof(AOpCodeSimdReg));
SetA64("0101111000101000000010xxxxxxxxxx", AInstEmit.Sha1h_V, typeof(AOpCodeSimd));
SetA64("01011110000xxxxx001000xxxxxxxxxx", AInstEmit.Sha1m_V, typeof(AOpCodeSimdReg));
SetA64("01011110000xxxxx000100xxxxxxxxxx", AInstEmit.Sha1p_V, typeof(AOpCodeSimdReg));
SetA64("01011110000xxxxx001100xxxxxxxxxx", AInstEmit.Sha1su0_V, typeof(AOpCodeSimdReg));
SetA64("0101111000101000000110xxxxxxxxxx", AInstEmit.Sha1su1_V, typeof(AOpCodeSimd));
SetA64("01011110000xxxxx010000xxxxxxxxxx", AInstEmit.Sha256h_V, typeof(AOpCodeSimdReg));
SetA64("01011110000xxxxx010100xxxxxxxxxx", AInstEmit.Sha256h2_V, typeof(AOpCodeSimdReg));
SetA64("0101111000101000001010xxxxxxxxxx", AInstEmit.Sha256su0_V, typeof(AOpCodeSimd));
SetA64("01011110000xxxxx011000xxxxxxxxxx", AInstEmit.Sha256su1_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Shadd_V, typeof(AOpCodeSimdReg));
SetA64("0101111101xxxxxx010101xxxxxxxxxx", AInstEmit.Shl_S, typeof(AOpCodeSimdShImm));
SetA64("0x00111100>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm));
SetA64("0100111101xxxxxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm));
SetA64("0x101110<<100001001110xxxxxxxxxx", AInstEmit.Shll_V, typeof(AOpCodeSimd));
SetA64("0x00111100>>>xxx100001xxxxxxxxxx", AInstEmit.Shrn_V, typeof(AOpCodeSimdShImm));
SetA64("0x001110<<1xxxxx001001xxxxxxxxxx", AInstEmit.Shsub_V, typeof(AOpCodeSimdReg));
SetA64("0x1011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Sli_V, typeof(AOpCodeSimdShImm));
SetA64("0x001110<<1xxxxx011001xxxxxxxxxx", AInstEmit.Smax_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx101001xxxxxxxxxx", AInstEmit.Smaxp_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx011011xxxxxxxxxx", AInstEmit.Smin_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx101011xxxxxxxxxx", AInstEmit.Sminp_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx100000xxxxxxxxxx", AInstEmit.Smlal_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx101000xxxxxxxxxx", AInstEmit.Smlsl_V, typeof(AOpCodeSimdReg));
SetA64("0x001110000xxxxx001011xxxxxxxxxx", AInstEmit.Smov_S, typeof(AOpCodeSimdIns));
SetA64("0x001110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Smull_V, typeof(AOpCodeSimdReg));
SetA64("01011110xx100000011110xxxxxxxxxx", AInstEmit.Sqabs_S, typeof(AOpCodeSimd));
SetA64("0>001110<<100000011110xxxxxxxxxx", AInstEmit.Sqabs_V, typeof(AOpCodeSimd));
SetA64("01011110xx1xxxxx000011xxxxxxxxxx", AInstEmit.Sqadd_S, typeof(AOpCodeSimdReg));
SetA64("0>001110<<1xxxxx000011xxxxxxxxxx", AInstEmit.Sqadd_V, typeof(AOpCodeSimdReg));
SetA64("01011110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_S, typeof(AOpCodeSimdReg));
SetA64("01011110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_S, typeof(AOpCodeSimdReg));
SetA64("0x001110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_V, typeof(AOpCodeSimdReg));
SetA64("0x001110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_V, typeof(AOpCodeSimdReg));
SetA64("01111110xx100000011110xxxxxxxxxx", AInstEmit.Sqneg_S, typeof(AOpCodeSimd));
SetA64("0>101110<<100000011110xxxxxxxxxx", AInstEmit.Sqneg_V, typeof(AOpCodeSimd));
SetA64("01111110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_S, typeof(AOpCodeSimdReg));
SetA64("01111110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_S, typeof(AOpCodeSimdReg));
SetA64("0x101110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_V, typeof(AOpCodeSimdReg));
SetA64("0x101110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_V, typeof(AOpCodeSimdReg));
SetA64("0101111100>>>xxx100111xxxxxxxxxx", AInstEmit.Sqrshrn_S, typeof(AOpCodeSimdShImm));
SetA64("0x00111100>>>xxx100111xxxxxxxxxx", AInstEmit.Sqrshrn_V, typeof(AOpCodeSimdShImm));
SetA64("0111111100>>>xxx100011xxxxxxxxxx", AInstEmit.Sqrshrun_S, typeof(AOpCodeSimdShImm));
SetA64("0x10111100>>>xxx100011xxxxxxxxxx", AInstEmit.Sqrshrun_V, typeof(AOpCodeSimdShImm));
SetA64("0101111100>>>xxx100101xxxxxxxxxx", AInstEmit.Sqshrn_S, typeof(AOpCodeSimdShImm));
SetA64("0x00111100>>>xxx100101xxxxxxxxxx", AInstEmit.Sqshrn_V, typeof(AOpCodeSimdShImm));
SetA64("0111111100>>>xxx100001xxxxxxxxxx", AInstEmit.Sqshrun_S, typeof(AOpCodeSimdShImm));
SetA64("0x10111100>>>xxx100001xxxxxxxxxx", AInstEmit.Sqshrun_V, typeof(AOpCodeSimdShImm));
SetA64("01011110xx1xxxxx001011xxxxxxxxxx", AInstEmit.Sqsub_S, typeof(AOpCodeSimdReg));
SetA64("0>001110<<1xxxxx001011xxxxxxxxxx", AInstEmit.Sqsub_V, typeof(AOpCodeSimdReg));
SetA64("01011110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_S, typeof(AOpCodeSimd));
SetA64("0x001110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_V, typeof(AOpCodeSimd));
SetA64("01111110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_S, typeof(AOpCodeSimd));
SetA64("0x101110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_V, typeof(AOpCodeSimd));
SetA64("0x001110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Srhadd_V, typeof(AOpCodeSimdReg));
SetA64("0101111101xxxxxx001001xxxxxxxxxx", AInstEmit.Srshr_S, typeof(AOpCodeSimdShImm));
SetA64("0x00111100>>>xxx001001xxxxxxxxxx", AInstEmit.Srshr_V, typeof(AOpCodeSimdShImm));
SetA64("0100111101xxxxxx001001xxxxxxxxxx", AInstEmit.Srshr_V, typeof(AOpCodeSimdShImm));
SetA64("0101111101xxxxxx001101xxxxxxxxxx", AInstEmit.Srsra_S, typeof(AOpCodeSimdShImm));
SetA64("0x00111100>>>xxx001101xxxxxxxxxx", AInstEmit.Srsra_V, typeof(AOpCodeSimdShImm));
SetA64("0100111101xxxxxx001101xxxxxxxxxx", AInstEmit.Srsra_V, typeof(AOpCodeSimdShImm));
SetA64("0>001110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Sshl_V, typeof(AOpCodeSimdReg));
SetA64("0x00111100>>>xxx101001xxxxxxxxxx", AInstEmit.Sshll_V, typeof(AOpCodeSimdShImm));
SetA64("0101111101xxxxxx000001xxxxxxxxxx", AInstEmit.Sshr_S, typeof(AOpCodeSimdShImm));
SetA64("0x00111100>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_V, typeof(AOpCodeSimdShImm));
SetA64("0100111101xxxxxx000001xxxxxxxxxx", AInstEmit.Sshr_V, typeof(AOpCodeSimdShImm));
SetA64("0101111101xxxxxx000101xxxxxxxxxx", AInstEmit.Ssra_S, typeof(AOpCodeSimdShImm));
SetA64("0x00111100>>>xxx000101xxxxxxxxxx", AInstEmit.Ssra_V, typeof(AOpCodeSimdShImm));
SetA64("0100111101xxxxxx000101xxxxxxxxxx", AInstEmit.Ssra_V, typeof(AOpCodeSimdShImm));
SetA64("0x001110<<1xxxxx001000xxxxxxxxxx", AInstEmit.Ssubl_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx001100xxxxxxxxxx", AInstEmit.Ssubw_V, typeof(AOpCodeSimdReg));
SetA64("0x00110000000000xxxxxxxxxxxxxxxx", AInstEmit.St__Vms, typeof(AOpCodeSimdMemMs));
SetA64("0x001100100xxxxxxxxxxxxxxxxxxxxx", AInstEmit.St__Vms, typeof(AOpCodeSimdMemMs));
SetA64("0x00110100x00000xxxxxxxxxxxxxxxx", AInstEmit.St__Vss, typeof(AOpCodeSimdMemSs));
SetA64("0x00110110xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.St__Vss, typeof(AOpCodeSimdMemSs));
SetA64("xx10110xx0xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Stp, typeof(AOpCodeSimdMemPair));
SetA64("xx111100x00xxxxxxxxx00xxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeSimdMemImm));
SetA64("xx111100x00xxxxxxxxx01xxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeSimdMemImm));
SetA64("xx111100x00xxxxxxxxx11xxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeSimdMemImm));
SetA64("xx111101x0xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeSimdMemImm));
SetA64("xx111100x01xxxxxxxxx10xxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeSimdMemReg));
SetA64("01111110111xxxxx100001xxxxxxxxxx", AInstEmit.Sub_S, typeof(AOpCodeSimdReg));
SetA64("0>101110<<1xxxxx100001xxxxxxxxxx", AInstEmit.Sub_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx011000xxxxxxxxxx", AInstEmit.Subhn_V, typeof(AOpCodeSimdReg));
SetA64("01011110xx100000001110xxxxxxxxxx", AInstEmit.Suqadd_S, typeof(AOpCodeSimd));
SetA64("0>001110<<100000001110xxxxxxxxxx", AInstEmit.Suqadd_V, typeof(AOpCodeSimd));
SetA64("0x001110000xxxxx0xx000xxxxxxxxxx", AInstEmit.Tbl_V, typeof(AOpCodeSimdTbl));
SetA64("0>001110<<0xxxxx001010xxxxxxxxxx", AInstEmit.Trn1_V, typeof(AOpCodeSimdReg));
SetA64("0>001110<<0xxxxx011010xxxxxxxxxx", AInstEmit.Trn2_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx011111xxxxxxxxxx", AInstEmit.Uaba_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx010100xxxxxxxxxx", AInstEmit.Uabal_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx011101xxxxxxxxxx", AInstEmit.Uabd_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Uabdl_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<100000011010xxxxxxxxxx", AInstEmit.Uadalp_V, typeof(AOpCodeSimd));
SetA64("0x101110<<1xxxxx000000xxxxxxxxxx", AInstEmit.Uaddl_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<100000001010xxxxxxxxxx", AInstEmit.Uaddlp_V, typeof(AOpCodeSimd));
SetA64("001011100x110000001110xxxxxxxxxx", AInstEmit.Uaddlv_V, typeof(AOpCodeSimd));
SetA64("01101110<<110000001110xxxxxxxxxx", AInstEmit.Uaddlv_V, typeof(AOpCodeSimd));
SetA64("0x101110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Uaddw_V, typeof(AOpCodeSimdReg));
SetA64("x0011110xx100011000000xxxxxxxxxx", AInstEmit.Ucvtf_Gp, typeof(AOpCodeSimdCvt));
SetA64("011111100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_S, typeof(AOpCodeSimd));
SetA64("0x1011100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_V, typeof(AOpCodeSimd));
SetA64("0x101110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Uhadd_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx001001xxxxxxxxxx", AInstEmit.Uhsub_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx011001xxxxxxxxxx", AInstEmit.Umax_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx101001xxxxxxxxxx", AInstEmit.Umaxp_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx011011xxxxxxxxxx", AInstEmit.Umin_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx101011xxxxxxxxxx", AInstEmit.Uminp_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx100000xxxxxxxxxx", AInstEmit.Umlal_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx101000xxxxxxxxxx", AInstEmit.Umlsl_V, typeof(AOpCodeSimdReg));
SetA64("0x001110000xxxxx001111xxxxxxxxxx", AInstEmit.Umov_S, typeof(AOpCodeSimdIns));
SetA64("0x101110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Umull_V, typeof(AOpCodeSimdReg));
SetA64("01111110xx1xxxxx000011xxxxxxxxxx", AInstEmit.Uqadd_S, typeof(AOpCodeSimdReg));
SetA64("0>101110<<1xxxxx000011xxxxxxxxxx", AInstEmit.Uqadd_V, typeof(AOpCodeSimdReg));
SetA64("0111111100>>>xxx100111xxxxxxxxxx", AInstEmit.Uqrshrn_S, typeof(AOpCodeSimdShImm));
SetA64("0x10111100>>>xxx100111xxxxxxxxxx", AInstEmit.Uqrshrn_V, typeof(AOpCodeSimdShImm));
SetA64("0111111100>>>xxx100101xxxxxxxxxx", AInstEmit.Uqshrn_S, typeof(AOpCodeSimdShImm));
SetA64("0x10111100>>>xxx100101xxxxxxxxxx", AInstEmit.Uqshrn_V, typeof(AOpCodeSimdShImm));
SetA64("01111110xx1xxxxx001011xxxxxxxxxx", AInstEmit.Uqsub_S, typeof(AOpCodeSimdReg));
SetA64("0>101110<<1xxxxx001011xxxxxxxxxx", AInstEmit.Uqsub_V, typeof(AOpCodeSimdReg));
SetA64("01111110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_S, typeof(AOpCodeSimd));
SetA64("0x101110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_V, typeof(AOpCodeSimd));
SetA64("0x101110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Urhadd_V, typeof(AOpCodeSimdReg));
SetA64("0111111101xxxxxx001001xxxxxxxxxx", AInstEmit.Urshr_S, typeof(AOpCodeSimdShImm));
SetA64("0x10111100>>>xxx001001xxxxxxxxxx", AInstEmit.Urshr_V, typeof(AOpCodeSimdShImm));
SetA64("0110111101xxxxxx001001xxxxxxxxxx", AInstEmit.Urshr_V, typeof(AOpCodeSimdShImm));
SetA64("0111111101xxxxxx001101xxxxxxxxxx", AInstEmit.Ursra_S, typeof(AOpCodeSimdShImm));
SetA64("0x10111100>>>xxx001101xxxxxxxxxx", AInstEmit.Ursra_V, typeof(AOpCodeSimdShImm));
SetA64("0110111101xxxxxx001101xxxxxxxxxx", AInstEmit.Ursra_V, typeof(AOpCodeSimdShImm));
SetA64("0>101110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Ushl_V, typeof(AOpCodeSimdReg));
SetA64("0x10111100>>>xxx101001xxxxxxxxxx", AInstEmit.Ushll_V, typeof(AOpCodeSimdShImm));
SetA64("0111111101xxxxxx000001xxxxxxxxxx", AInstEmit.Ushr_S, typeof(AOpCodeSimdShImm));
SetA64("0x10111100>>>xxx000001xxxxxxxxxx", AInstEmit.Ushr_V, typeof(AOpCodeSimdShImm));
SetA64("0110111101xxxxxx000001xxxxxxxxxx", AInstEmit.Ushr_V, typeof(AOpCodeSimdShImm));
SetA64("01111110xx100000001110xxxxxxxxxx", AInstEmit.Usqadd_S, typeof(AOpCodeSimd));
SetA64("0>101110<<100000001110xxxxxxxxxx", AInstEmit.Usqadd_V, typeof(AOpCodeSimd));
SetA64("0111111101xxxxxx000101xxxxxxxxxx", AInstEmit.Usra_S, typeof(AOpCodeSimdShImm));
SetA64("0x10111100>>>xxx000101xxxxxxxxxx", AInstEmit.Usra_V, typeof(AOpCodeSimdShImm));
SetA64("0110111101xxxxxx000101xxxxxxxxxx", AInstEmit.Usra_V, typeof(AOpCodeSimdShImm));
SetA64("0x101110<<1xxxxx001000xxxxxxxxxx", AInstEmit.Usubl_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx001100xxxxxxxxxx", AInstEmit.Usubw_V, typeof(AOpCodeSimdReg));
SetA64("0>001110<<0xxxxx000110xxxxxxxxxx", AInstEmit.Uzp1_V, typeof(AOpCodeSimdReg));
SetA64("0>001110<<0xxxxx010110xxxxxxxxxx", AInstEmit.Uzp2_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<100001001010xxxxxxxxxx", AInstEmit.Xtn_V, typeof(AOpCodeSimd));
SetA64("0>001110<<0xxxxx001110xxxxxxxxxx", AInstEmit.Zip1_V, typeof(AOpCodeSimdReg));
SetA64("0>001110<<0xxxxx011110xxxxxxxxxx", AInstEmit.Zip2_V, typeof(AOpCodeSimdReg));
#endregion
#region "Generate InstA64FastLookup Table (AArch64)"
var tmp = new List<InstInfo>[_fastLookupSize];
for (int i = 0; i < _fastLookupSize; i++)
{
tmp[i] = new List<InstInfo>();
}
foreach (var inst in _allInstA64)
{
int mask = ToFastLookupIndex(inst.Mask);
int value = ToFastLookupIndex(inst.Value);
for (int i = 0; i < _fastLookupSize; i++)
{
if ((i & mask) == value)
{
tmp[i].Add(inst);
}
}
}
for (int i = 0; i < _fastLookupSize; i++)
{
_instA64FastLookup[i] = tmp[i].ToArray();
}
#endregion
}
private class InstInfo
{
public int Mask;
public int Value;
public AInst Inst;
public InstInfo(int mask, int value, AInst inst)
{
Mask = mask;
Value = value;
Inst = inst;
}
}
private static List<InstInfo> _allInstA32 = new List<InstInfo>();
private static List<InstInfo> _allInstA64 = new List<InstInfo>();
private static int _fastLookupSize = 0x1000;
private static InstInfo[][] _instA64FastLookup = new InstInfo[_fastLookupSize][];
private static void SetA32(string encoding, AInstInterpreter interpreter, Type type)
{
Set(encoding, new AInst(interpreter, null, type), AExecutionMode.AArch32);
}
private static void SetA64(string encoding, AInstEmitter emitter, Type type)
{
Set(encoding, new AInst(null, emitter, type), AExecutionMode.AArch64);
}
private static void Set(string encoding, AInst inst, AExecutionMode mode)
{
int bit = encoding.Length - 1;
int value = 0;
int xMask = 0;
int xBits = 0;
int[] xPos = new int[encoding.Length];
int blacklisted = 0;
for (int index = 0; index < encoding.Length; index++, bit--)
{
//Note: < and > are used on special encodings.
//The < means that we should never have ALL bits with the '<' set.
//So, when the encoding has <<, it means that 00, 01, and 10 are valid,
//but not 11. <<< is 000, 001, ..., 110 but NOT 111, and so on...
//For >, the invalid value is zero. So, for >> 01, 10 and 11 are valid,
//but 00 isn't.
char chr = encoding[index];
if (chr == '1')
{
value |= 1 << bit;
}
else if (chr == 'x')
{
xMask |= 1 << bit;
}
else if (chr == '>')
{
xPos[xBits++] = bit;
}
else if (chr == '<')
{
xPos[xBits++] = bit;
blacklisted |= 1 << bit;
}
else if (chr != '0')
{
throw new ArgumentException(nameof(encoding));
}
}
xMask = ~xMask;
if (xBits == 0)
{
InsertInst(xMask, value, inst, mode);
return;
}
for (int index = 0; index < (1 << xBits); index++)
{
int mask = 0;
for (int x = 0; x < xBits; x++)
{
mask |= ((index >> x) & 1) << xPos[x];
}
if (mask != blacklisted)
{
InsertInst(xMask, value | mask, inst, mode);
}
}
}
private static void InsertInst(
int xMask,
int value,
AInst inst,
AExecutionMode mode)
{
InstInfo info = new InstInfo(xMask, value, inst);
if (mode == AExecutionMode.AArch64)
{
_allInstA64.Add(info);
}
else
{
_allInstA32.Add(info);
}
}
public static AInst GetInstA32(int opCode)
{
return GetInstFromList(_allInstA32, opCode);
}
public static AInst GetInstA64(int opCode)
{
return GetInstFromList(_instA64FastLookup[ToFastLookupIndex(opCode)], opCode);
}
private static int ToFastLookupIndex(int value)
{
return ((value >> 10) & 0x00F) | ((value >> 18) & 0xFF0);
}
private static AInst GetInstFromList(IEnumerable<InstInfo> instList, int opCode)
{
foreach (var node in instList)
{
if ((opCode & node.Mask) == node.Value)
{
return node.Inst;
}
}
return AInst.Undefined;
}
}
}

6
ChocolArm64/AThread.cs
View file

@ -10,7 +10,7 @@ namespace ChocolArm64
public AThreadState ThreadState { get; private set; } public AThreadState ThreadState { get; private set; }
public AMemory Memory { get; private set; } public AMemory Memory { get; private set; }
private ATranslator _translator; private Translator _translator;
public Thread Work; public Thread Work;
@ -18,14 +18,14 @@ namespace ChocolArm64
private int _isExecuting; private int _isExecuting;
public AThread(ATranslator translator, AMemory memory, long entryPoint) public AThread(Translator translator, AMemory memory, long entryPoint)
{ {
_translator = translator; _translator = translator;
Memory = memory; Memory = memory;
ThreadState = new AThreadState(); ThreadState = new AThreadState();
ThreadState.ExecutionMode = AExecutionMode.AArch64; ThreadState.ExecutionMode = ExecutionMode.AArch64;
ThreadState.Running = true; ThreadState.Running = true;

2
ChocolArm64/ABitUtils.cs → ChocolArm64/BitUtils.cs
View file

@ -1,6 +1,6 @@
namespace ChocolArm64 namespace ChocolArm64
{ {
static class ABitUtils static class BitUtils
{ {
public static int HighestBitSet32(int value) public static int HighestBitSet32(int value)
{ {

70
ChocolArm64/Decoder/ADecoder.cs
View file

@ -10,7 +10,7 @@ namespace ChocolArm64.Decoder
{ {
static class ADecoder static class ADecoder
{ {
private delegate object OpActivator(AInst inst, long position, int opCode); private delegate object OpActivator(Inst inst, long position, int opCode);
private static ConcurrentDictionary<Type, OpActivator> _opActivators; private static ConcurrentDictionary<Type, OpActivator> _opActivators;
@ -19,31 +19,31 @@ namespace ChocolArm64.Decoder
_opActivators = new ConcurrentDictionary<Type, OpActivator>(); _opActivators = new ConcurrentDictionary<Type, OpActivator>();
} }
public static ABlock DecodeBasicBlock(AThreadState state, AMemory memory, long start) public static Block DecodeBasicBlock(AThreadState state, AMemory memory, long start)
{ {
ABlock block = new ABlock(start); Block block = new Block(start);
FillBlock(state, memory, block); FillBlock(state, memory, block);
return block; return block;
} }
public static (ABlock[] Graph, ABlock Root) DecodeSubroutine( public static (Block[] Graph, Block Root) DecodeSubroutine(
ATranslatorCache cache, TranslatorCache cache,
AThreadState state, AThreadState state,
AMemory memory, AMemory memory,
long start) long start)
{ {
Dictionary<long, ABlock> visited = new Dictionary<long, ABlock>(); Dictionary<long, Block> visited = new Dictionary<long, Block>();
Dictionary<long, ABlock> visitedEnd = new Dictionary<long, ABlock>(); Dictionary<long, Block> visitedEnd = new Dictionary<long, Block>();
Queue<ABlock> blocks = new Queue<ABlock>(); Queue<Block> blocks = new Queue<Block>();
ABlock Enqueue(long position) Block Enqueue(long position)
{ {
if (!visited.TryGetValue(position, out ABlock output)) if (!visited.TryGetValue(position, out Block output))
{ {
output = new ABlock(position); output = new Block(position);
blocks.Enqueue(output); blocks.Enqueue(output);
@ -53,11 +53,11 @@ namespace ChocolArm64.Decoder
return output; return output;
} }
ABlock root = Enqueue(start); Block root = Enqueue(start);
while (blocks.Count > 0) while (blocks.Count > 0)
{ {
ABlock current = blocks.Dequeue(); Block current = blocks.Dequeue();
FillBlock(state, memory, current); FillBlock(state, memory, current);
@ -71,9 +71,9 @@ namespace ChocolArm64.Decoder
AOpCode lastOp = current.GetLastOp(); AOpCode lastOp = current.GetLastOp();
if (lastOp is AOpCodeBImm op) if (lastOp is OpCodeBImm op)
{ {
if (op.Emitter == AInstEmit.Bl) if (op.Emitter == InstEmit.Bl)
{ {
hasCachedSub = cache.HasSubroutine(op.Imm); hasCachedSub = cache.HasSubroutine(op.Imm);
} }
@ -83,8 +83,8 @@ namespace ChocolArm64.Decoder
} }
} }
if (!((lastOp is AOpCodeBImmAl) || if (!((lastOp is OpCodeBImmAl) ||
(lastOp is AOpCodeBReg)) || hasCachedSub) (lastOp is OpCodeBReg)) || hasCachedSub)
{ {
current.Next = Enqueue(current.EndPosition); current.Next = Enqueue(current.EndPosition);
} }
@ -94,11 +94,11 @@ namespace ChocolArm64.Decoder
//then we need to split the bigger block and have two small blocks, //then we need to split the bigger block and have two small blocks,
//the end position of the bigger "Current" block should then be == to //the end position of the bigger "Current" block should then be == to
//the position of the "Smaller" block. //the position of the "Smaller" block.
while (visitedEnd.TryGetValue(current.EndPosition, out ABlock smaller)) while (visitedEnd.TryGetValue(current.EndPosition, out Block smaller))
{ {
if (current.Position > smaller.Position) if (current.Position > smaller.Position)
{ {
ABlock temp = smaller; Block temp = smaller;
smaller = current; smaller = current;
current = temp; current = temp;
@ -119,19 +119,19 @@ namespace ChocolArm64.Decoder
} }
//Make and sort Graph blocks array by position. //Make and sort Graph blocks array by position.
ABlock[] graph = new ABlock[visited.Count]; Block[] graph = new Block[visited.Count];
while (visited.Count > 0) while (visited.Count > 0)
{ {
ulong firstPos = ulong.MaxValue; ulong firstPos = ulong.MaxValue;
foreach (ABlock block in visited.Values) foreach (Block block in visited.Values)
{ {
if (firstPos > (ulong)block.Position) if (firstPos > (ulong)block.Position)
firstPos = (ulong)block.Position; firstPos = (ulong)block.Position;
} }
ABlock current = visited[(long)firstPos]; Block current = visited[(long)firstPos];
do do
{ {
@ -147,7 +147,7 @@ namespace ChocolArm64.Decoder
return (graph, root); return (graph, root);
} }
private static void FillBlock(AThreadState state, AMemory memory, ABlock block) private static void FillBlock(AThreadState state, AMemory memory, Block block)
{ {
long position = block.Position; long position = block.Position;
@ -170,34 +170,34 @@ namespace ChocolArm64.Decoder
private static bool IsBranch(AOpCode opCode) private static bool IsBranch(AOpCode opCode)
{ {
return opCode is AOpCodeBImm || return opCode is OpCodeBImm ||
opCode is AOpCodeBReg; opCode is OpCodeBReg;
} }
private static bool IsException(AOpCode opCode) private static bool IsException(AOpCode opCode)
{ {
return opCode.Emitter == AInstEmit.Brk || return opCode.Emitter == InstEmit.Brk ||
opCode.Emitter == AInstEmit.Svc || opCode.Emitter == InstEmit.Svc ||
opCode.Emitter == AInstEmit.Und; opCode.Emitter == InstEmit.Und;
} }
public static AOpCode DecodeOpCode(AThreadState state, AMemory memory, long position) public static AOpCode DecodeOpCode(AThreadState state, AMemory memory, long position)
{ {
int opCode = memory.ReadInt32(position); int opCode = memory.ReadInt32(position);
AInst inst; Inst inst;
if (state.ExecutionMode == AExecutionMode.AArch64) if (state.ExecutionMode == ExecutionMode.AArch64)
{ {
inst = AOpCodeTable.GetInstA64(opCode); inst = OpCodeTable.GetInstA64(opCode);
} }
else else
{ {
//TODO: Thumb support. //TODO: Thumb support.
inst = AOpCodeTable.GetInstA32(opCode); inst = OpCodeTable.GetInstA32(opCode);
} }
AOpCode decodedOpCode = new AOpCode(AInst.Undefined, position, opCode); AOpCode decodedOpCode = new AOpCode(Inst.Undefined, position, opCode);
if (inst.Type != null) if (inst.Type != null)
{ {
@ -207,7 +207,7 @@ namespace ChocolArm64.Decoder
return decodedOpCode; return decodedOpCode;
} }
private static AOpCode MakeOpCode(Type type, AInst inst, long position, int opCode) private static AOpCode MakeOpCode(Type type, Inst inst, long position, int opCode)
{ {
if (type == null) if (type == null)
{ {
@ -221,7 +221,7 @@ namespace ChocolArm64.Decoder
private static OpActivator CacheOpActivator(Type type) private static OpActivator CacheOpActivator(Type type)
{ {
Type[] argTypes = new Type[] { typeof(AInst), typeof(long), typeof(int) }; Type[] argTypes = new Type[] { typeof(Inst), typeof(long), typeof(int) };
DynamicMethod mthd = new DynamicMethod($"Make{type.Name}", type, argTypes); DynamicMethod mthd = new DynamicMethod($"Make{type.Name}", type, argTypes);

20
ChocolArm64/Decoder/AOpCode.cs
View file

@ -4,21 +4,21 @@ using System;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCode : IaOpCode class AOpCode : IOpCode
{ {
public long Position { get; private set; } public long Position { get; private set; }
public int RawOpCode { get; private set; } public int RawOpCode { get; private set; }
public AInstEmitter Emitter { get; protected set; } public InstEmitter Emitter { get; protected set; }
public AInstInterpreter Interpreter { get; protected set; } public InstInterpreter Interpreter { get; protected set; }
public ARegisterSize RegisterSize { get; protected set; } public RegisterSize RegisterSize { get; protected set; }
public AOpCode(AInst inst, long position, int opCode) public AOpCode(Inst inst, long position, int opCode)
{ {
Position = position; Position = position;
RawOpCode = opCode; RawOpCode = opCode;
RegisterSize = ARegisterSize.Int64; RegisterSize = RegisterSize.Int64;
Emitter = inst.Emitter; Emitter = inst.Emitter;
Interpreter = inst.Interpreter; Interpreter = inst.Interpreter;
@ -28,10 +28,10 @@ namespace ChocolArm64.Decoder
{ {
switch (RegisterSize) switch (RegisterSize)
{ {
case ARegisterSize.Int32: return 32; case RegisterSize.Int32: return 32;
case ARegisterSize.Int64: return 64; case RegisterSize.Int64: return 64;
case ARegisterSize.Simd64: return 64; case RegisterSize.Simd64: return 64;
case ARegisterSize.Simd128: return 128; case RegisterSize.Simd128: return 128;
} }
throw new InvalidOperationException(); throw new InvalidOperationException();

11
ChocolArm64/Decoder/AOpCodeBImm.cs
View file

@ -1,11 +0,0 @@
using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class AOpCodeBImm : AOpCode
{
public long Imm { get; protected set; }
public AOpCodeBImm(AInst inst, long position, int opCode) : base(inst, position, opCode) { }
}
}

12
ChocolArm64/Decoder/AOpCodeBImmAl.cs
View file

@ -1,12 +0,0 @@
using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class AOpCodeBImmAl : AOpCodeBImm
{
public AOpCodeBImmAl(AInst inst, long position, int opCode) : base(inst, position, opCode)
{
Imm = position + ADecoderHelper.DecodeImm26_2(opCode);
}
}
}

21
ChocolArm64/Decoder/AOpCodeBImmCmp.cs
View file

@ -1,21 +0,0 @@
using ChocolArm64.Instruction;
using ChocolArm64.State;
namespace ChocolArm64.Decoder
{
class AOpCodeBImmCmp : AOpCodeBImm
{
public int Rt { get; private set; }
public AOpCodeBImmCmp(AInst inst, long position, int opCode) : base(inst, position, opCode)
{
Rt = opCode & 0x1f;
Imm = position + ADecoderHelper.DecodeImmS19_2(opCode);
RegisterSize = (opCode >> 31) != 0
? ARegisterSize.Int64
: ARegisterSize.Int32;
}
}
}

25
ChocolArm64/Decoder/AOpCodeBImmCond.cs
View file

@ -1,25 +0,0 @@
using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class AOpCodeBImmCond : AOpCodeBImm, IaOpCodeCond
{
public ACond Cond { get; private set; }
public AOpCodeBImmCond(AInst inst, long position, int opCode) : base(inst, position, opCode)
{
int o0 = (opCode >> 4) & 1;
if (o0 != 0)
{
Emitter = AInstEmit.Und;
return;
}
Cond = (ACond)(opCode & 0xf);
Imm = position + ADecoderHelper.DecodeImmS19_2(opCode);
}
}
}

11
ChocolArm64/Decoder/AOpCodeCcmpImm.cs
View file

@ -1,11 +0,0 @@
using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class AOpCodeCcmpImm : AOpCodeCcmp, IaOpCodeAluImm
{
public long Imm => RmImm;
public AOpCodeCcmpImm(AInst inst, long position, int opCode) : base(inst, position, opCode) { }
}
}

15
ChocolArm64/Decoder/AOpCodeCcmpReg.cs
View file

@ -1,15 +0,0 @@
using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class AOpCodeCcmpReg : AOpCodeCcmp, IaOpCodeAluRs
{
public int Rm => RmImm;
public int Shift => 0;
public AShiftType ShiftType => AShiftType.Lsl;
public AOpCodeCcmpReg(AInst inst, long position, int opCode) : base(inst, position, opCode) { }
}
}

17
ChocolArm64/Decoder/AOpCodeCsel.cs
View file

@ -1,17 +0,0 @@
using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class AOpCodeCsel : AOpCodeAlu, IaOpCodeCond
{
public int Rm { get; private set; }
public ACond Cond { get; private set; }
public AOpCodeCsel(AInst inst, long position, int opCode) : base(inst, position, opCode)
{
Rm = (opCode >> 16) & 0x1f;
Cond = (ACond)((opCode >> 12) & 0xf);
}
}
}

17
ChocolArm64/Decoder/AOpCodeSimdFcond.cs
View file

@ -1,17 +0,0 @@
using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class AOpCodeSimdFcond : AOpCodeSimdReg, IaOpCodeCond
{
public int Nzcv { get; private set; }
public ACond Cond { get; private set; }
public AOpCodeSimdFcond(AInst inst, long position, int opCode) : base(inst, position, opCode)
{
Nzcv = (opCode >> 0) & 0xf;
Cond = (ACond)((opCode >> 12) & 0xf);
}
}
}

16
ChocolArm64/Decoder/AOpCodeSimdShImm.cs
View file

@ -1,16 +0,0 @@
using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class AOpCodeSimdShImm : AOpCodeSimd
{
public int Imm { get; private set; }
public AOpCodeSimdShImm(AInst inst, long position, int opCode) : base(inst, position, opCode)
{
Imm = (opCode >> 16) & 0x7f;
Size = ABitUtils.HighestBitSetNibble(Imm >> 3);
}
}
}

10
ChocolArm64/Decoder/ABlock.cs → ChocolArm64/Decoder/Block.cs
View file

@ -2,22 +2,22 @@ using System.Collections.Generic;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class ABlock class Block
{ {
public long Position { get; set; } public long Position { get; set; }
public long EndPosition { get; set; } public long EndPosition { get; set; }
public ABlock Next { get; set; } public Block Next { get; set; }
public ABlock Branch { get; set; } public Block Branch { get; set; }
public List<AOpCode> OpCodes { get; private set; } public List<AOpCode> OpCodes { get; private set; }
public ABlock() public Block()
{ {
OpCodes = new List<AOpCode>(); OpCodes = new List<AOpCode>();
} }
public ABlock(long position) : this() public Block(long position) : this()
{ {
Position = position; Position = position;
} }

2
ChocolArm64/Decoder/ACond.cs → ChocolArm64/Decoder/Cond.cs
View file

@ -1,6 +1,6 @@
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
enum ACond enum Cond
{ {
Eq = 0, Eq = 0,
Ne = 1, Ne = 1,

2
ChocolArm64/Decoder/ADataOp.cs → ChocolArm64/Decoder/DataOp.cs
View file

@ -1,6 +1,6 @@
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
enum ADataOp enum DataOp
{ {
Adr = 0, Adr = 0,
Arithmetic = 1, Arithmetic = 1,

16
ChocolArm64/Decoder/ADecoderHelper.cs → ChocolArm64/Decoder/DecoderHelper.cs
View file

@ -2,7 +2,7 @@ using System;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
static class ADecoderHelper static class DecoderHelper
{ {
public struct BitMask public struct BitMask
{ {
@ -23,7 +23,7 @@ namespace ChocolArm64.Decoder
int n = (opCode >> 22) & 1; int n = (opCode >> 22) & 1;
int sf = (opCode >> 31) & 1; int sf = (opCode >> 31) & 1;
int length = ABitUtils.HighestBitSet32((~immS & 0x3f) | (n << 6)); int length = BitUtils.HighestBitSet32((~immS & 0x3f) | (n << 6));
if (length < 1 || (sf == 0 && n != 0)) if (length < 1 || (sf == 0 && n != 0))
{ {
@ -42,19 +42,19 @@ namespace ChocolArm64.Decoder
return BitMask.Invalid; return BitMask.Invalid;
} }
long wMask = ABitUtils.FillWithOnes(s + 1); long wMask = BitUtils.FillWithOnes(s + 1);
long tMask = ABitUtils.FillWithOnes(((s - r) & levels) + 1); long tMask = BitUtils.FillWithOnes(((s - r) & levels) + 1);
if (r > 0) if (r > 0)
{ {
wMask = ABitUtils.RotateRight(wMask, r, size); wMask = BitUtils.RotateRight(wMask, r, size);
wMask &= ABitUtils.FillWithOnes(size); wMask &= BitUtils.FillWithOnes(size);
} }
return new BitMask() return new BitMask()
{ {
WMask = ABitUtils.Replicate(wMask, size), WMask = BitUtils.Replicate(wMask, size),
TMask = ABitUtils.Replicate(tMask, size), TMask = BitUtils.Replicate(tMask, size),
Pos = immS, Pos = immS,
Shift = immR Shift = immR

7
ChocolArm64/Decoder/IAOpCodeCond.cs
View file

@ -1,7 +0,0 @@
namespace ChocolArm64.Decoder
{
interface IaOpCodeCond : IaOpCode
{
ACond Cond { get; }
}
}

6
ChocolArm64/Decoder/IAOpCode.cs → ChocolArm64/Decoder/IOpCode.cs
View file

@ -3,11 +3,11 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
interface IaOpCode interface IOpCode
{ {
long Position { get; } long Position { get; }
AInstEmitter Emitter { get; } InstEmitter Emitter { get; }
ARegisterSize RegisterSize { get; } RegisterSize RegisterSize { get; }
} }
} }

4
ChocolArm64/Decoder/IAOpCodeAlu.cs → ChocolArm64/Decoder/IOpCodeAlu.cs
View file

@ -1,10 +1,10 @@
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
interface IaOpCodeAlu : IaOpCode interface IOpCodeAlu : IOpCode
{ {
int Rd { get; } int Rd { get; }
int Rn { get; } int Rn { get; }
ADataOp DataOp { get; } DataOp DataOp { get; }
} }
} }

2
ChocolArm64/Decoder/IAOpCodeAluImm.cs → ChocolArm64/Decoder/IOpCodeAluImm.cs
View file

@ -1,6 +1,6 @@
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
interface IaOpCodeAluImm : IaOpCodeAlu interface IOpCodeAluImm : IOpCodeAlu
{ {
long Imm { get; } long Imm { get; }
} }

4
ChocolArm64/Decoder/IAOpCodeAluRs.cs → ChocolArm64/Decoder/IOpCodeAluRs.cs
View file

@ -1,10 +1,10 @@
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
interface IaOpCodeAluRs : IaOpCodeAlu interface IOpCodeAluRs : IOpCodeAlu
{ {
int Shift { get; } int Shift { get; }
int Rm { get; } int Rm { get; }
AShiftType ShiftType { get; } ShiftType ShiftType { get; }
} }
} }

4
ChocolArm64/Decoder/IAOpCodeAluRx.cs → ChocolArm64/Decoder/IOpCodeAluRx.cs
View file

@ -1,10 +1,10 @@
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
interface IaOpCodeAluRx : IaOpCodeAlu interface IOpCodeAluRx : IOpCodeAlu
{ {
int Shift { get; } int Shift { get; }
int Rm { get; } int Rm { get; }
AIntType IntType { get; } IntType IntType { get; }
} }
} }

7
ChocolArm64/Decoder/IOpCodeCond.cs Normal file
View file

@ -0,0 +1,7 @@
namespace ChocolArm64.Decoder
{
interface IOpCodeCond : IOpCode
{
Cond Cond { get; }
}
}

2
ChocolArm64/Decoder/IAOpCodeLit.cs → ChocolArm64/Decoder/IOpCodeLit.cs
View file

@ -1,6 +1,6 @@
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
interface IaOpCodeLit : IaOpCode interface IOpCodeLit : IOpCode
{ {
int Rt { get; } int Rt { get; }
long Imm { get; } long Imm { get; }

2
ChocolArm64/Decoder/IAOpCodeSimd.cs → ChocolArm64/Decoder/IOpCodeSimd.cs
View file

@ -1,6 +1,6 @@
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
interface IaOpCodeSimd : IaOpCode interface IOpCodeSimd : IOpCode
{ {
int Size { get; } int Size { get; }
} }

2
ChocolArm64/Decoder/AIntType.cs → ChocolArm64/Decoder/IntType.cs
View file

@ -1,6 +1,6 @@
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
enum AIntType enum IntType
{ {
UInt8 = 0, UInt8 = 0,
UInt16 = 1, UInt16 = 1,

6
ChocolArm64/Decoder/AOpCodeAdr.cs → ChocolArm64/Decoder/OpCodeAdr.cs
View file

@ -2,16 +2,16 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeAdr : AOpCode class OpCodeAdr : AOpCode
{ {
public int Rd { get; private set; } public int Rd { get; private set; }
public long Imm { get; private set; } public long Imm { get; private set; }
public AOpCodeAdr(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeAdr(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rd = opCode & 0x1f; Rd = opCode & 0x1f;
Imm = ADecoderHelper.DecodeImmS19_2(opCode); Imm = DecoderHelper.DecodeImmS19_2(opCode);
Imm |= ((long)opCode >> 29) & 3; Imm |= ((long)opCode >> 29) & 3;
} }
} }

12
ChocolArm64/Decoder/AOpCodeAlu.cs → ChocolArm64/Decoder/OpCodeAlu.cs
View file

@ -3,22 +3,22 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeAlu : AOpCode, IaOpCodeAlu class OpCodeAlu : AOpCode, IOpCodeAlu
{ {
public int Rd { get; protected set; } public int Rd { get; protected set; }
public int Rn { get; private set; } public int Rn { get; private set; }
public ADataOp DataOp { get; private set; } public DataOp DataOp { get; private set; }
public AOpCodeAlu(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeAlu(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rd = (opCode >> 0) & 0x1f; Rd = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f; Rn = (opCode >> 5) & 0x1f;
DataOp = (ADataOp)((opCode >> 24) & 0x3); DataOp = (DataOp)((opCode >> 24) & 0x3);
RegisterSize = (opCode >> 31) != 0 RegisterSize = (opCode >> 31) != 0
? ARegisterSize.Int64 ? State.RegisterSize.Int64
: ARegisterSize.Int32; : State.RegisterSize.Int32;
} }
} }
} }

12
ChocolArm64/Decoder/AOpCodeAluImm.cs → ChocolArm64/Decoder/OpCodeAluImm.cs
View file

@ -3,13 +3,13 @@ using System;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeAluImm : AOpCodeAlu, IaOpCodeAluImm class OpCodeAluImm : OpCodeAlu, IOpCodeAluImm
{ {
public long Imm { get; private set; } public long Imm { get; private set; }
public AOpCodeAluImm(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeAluImm(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
if (DataOp == ADataOp.Arithmetic) if (DataOp == DataOp.Arithmetic)
{ {
Imm = (opCode >> 10) & 0xfff; Imm = (opCode >> 10) & 0xfff;
@ -17,13 +17,13 @@ namespace ChocolArm64.Decoder
Imm <<= shift * 12; Imm <<= shift * 12;
} }
else if (DataOp == ADataOp.Logical) else if (DataOp == DataOp.Logical)
{ {
var bm = ADecoderHelper.DecodeBitMask(opCode, true); var bm = DecoderHelper.DecodeBitMask(opCode, true);
if (bm.IsUndefined) if (bm.IsUndefined)
{ {
Emitter = AInstEmit.Und; Emitter = InstEmit.Und;
return; return;
} }

10
ChocolArm64/Decoder/AOpCodeAluRs.cs → ChocolArm64/Decoder/OpCodeAluRs.cs
View file

@ -2,20 +2,20 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeAluRs : AOpCodeAlu, IaOpCodeAluRs class OpCodeAluRs : OpCodeAlu, IOpCodeAluRs
{ {
public int Shift { get; private set; } public int Shift { get; private set; }
public int Rm { get; private set; } public int Rm { get; private set; }
public AShiftType ShiftType { get; private set; } public ShiftType ShiftType { get; private set; }
public AOpCodeAluRs(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeAluRs(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
int shift = (opCode >> 10) & 0x3f; int shift = (opCode >> 10) & 0x3f;
if (shift >= GetBitsCount()) if (shift >= GetBitsCount())
{ {
Emitter = AInstEmit.Und; Emitter = InstEmit.Und;
return; return;
} }
@ -23,7 +23,7 @@ namespace ChocolArm64.Decoder
Shift = shift; Shift = shift;
Rm = (opCode >> 16) & 0x1f; Rm = (opCode >> 16) & 0x1f;
ShiftType = (AShiftType)((opCode >> 22) & 0x3); ShiftType = (ShiftType)((opCode >> 22) & 0x3);
} }
} }
} }

8
ChocolArm64/Decoder/AOpCodeAluRx.cs → ChocolArm64/Decoder/OpCodeAluRx.cs
View file

@ -2,17 +2,17 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeAluRx : AOpCodeAlu, IaOpCodeAluRx class OpCodeAluRx : OpCodeAlu, IOpCodeAluRx
{ {
public int Shift { get; private set; } public int Shift { get; private set; }
public int Rm { get; private set; } public int Rm { get; private set; }
public AIntType IntType { get; private set; } public IntType IntType { get; private set; }
public AOpCodeAluRx(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeAluRx(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Shift = (opCode >> 10) & 0x7; Shift = (opCode >> 10) & 0x7;
IntType = (AIntType)((opCode >> 13) & 0x7); IntType = (IntType)((opCode >> 13) & 0x7);
Rm = (opCode >> 16) & 0x1f; Rm = (opCode >> 16) & 0x1f;
} }
} }

11
ChocolArm64/Decoder/OpCodeBImm.cs Normal file
View file

@ -0,0 +1,11 @@
using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class OpCodeBImm : AOpCode
{
public long Imm { get; protected set; }
public OpCodeBImm(Inst inst, long position, int opCode) : base(inst, position, opCode) { }
}
}

12
ChocolArm64/Decoder/OpCodeBImmAl.cs Normal file
View file

@ -0,0 +1,12 @@
using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class OpCodeBImmAl : OpCodeBImm
{
public OpCodeBImmAl(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Imm = position + DecoderHelper.DecodeImm26_2(opCode);
}
}
}

21
ChocolArm64/Decoder/OpCodeBImmCmp.cs Normal file
View file

@ -0,0 +1,21 @@
using ChocolArm64.Instruction;
using ChocolArm64.State;
namespace ChocolArm64.Decoder
{
class OpCodeBImmCmp : OpCodeBImm
{
public int Rt { get; private set; }
public OpCodeBImmCmp(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rt = opCode & 0x1f;
Imm = position + DecoderHelper.DecodeImmS19_2(opCode);
RegisterSize = (opCode >> 31) != 0
? State.RegisterSize.Int64
: State.RegisterSize.Int32;
}
}
}

25
ChocolArm64/Decoder/OpCodeBImmCond.cs Normal file
View file

@ -0,0 +1,25 @@
using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class OpCodeBImmCond : OpCodeBImm, IOpCodeCond
{
public Cond Cond { get; private set; }
public OpCodeBImmCond(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
int o0 = (opCode >> 4) & 1;
if (o0 != 0)
{
Emitter = InstEmit.Und;
return;
}
Cond = (Cond)(opCode & 0xf);
Imm = position + DecoderHelper.DecodeImmS19_2(opCode);
}
}
}

6
ChocolArm64/Decoder/AOpCodeBImmTest.cs → ChocolArm64/Decoder/OpCodeBImmTest.cs
View file

@ -2,16 +2,16 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeBImmTest : AOpCodeBImm class OpCodeBImmTest : OpCodeBImm
{ {
public int Rt { get; private set; } public int Rt { get; private set; }
public int Pos { get; private set; } public int Pos { get; private set; }
public AOpCodeBImmTest(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeBImmTest(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rt = opCode & 0x1f; Rt = opCode & 0x1f;
Imm = position + ADecoderHelper.DecodeImmS14_2(opCode); Imm = position + DecoderHelper.DecodeImmS14_2(opCode);
Pos = (opCode >> 19) & 0x1f; Pos = (opCode >> 19) & 0x1f;
Pos |= (opCode >> 26) & 0x20; Pos |= (opCode >> 26) & 0x20;

6
ChocolArm64/Decoder/AOpCodeBReg.cs → ChocolArm64/Decoder/OpCodeBReg.cs
View file

@ -2,18 +2,18 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeBReg : AOpCode class OpCodeBReg : AOpCode
{ {
public int Rn { get; private set; } public int Rn { get; private set; }
public AOpCodeBReg(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeBReg(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
int op4 = (opCode >> 0) & 0x1f; int op4 = (opCode >> 0) & 0x1f;
int op2 = (opCode >> 16) & 0x1f; int op2 = (opCode >> 16) & 0x1f;
if (op2 != 0b11111 || op4 != 0b00000) if (op2 != 0b11111 || op4 != 0b00000)
{ {
Emitter = AInstEmit.Und; Emitter = InstEmit.Und;
return; return;
} }

8
ChocolArm64/Decoder/AOpCodeBfm.cs → ChocolArm64/Decoder/OpCodeBfm.cs
View file

@ -2,20 +2,20 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeBfm : AOpCodeAlu class OpCodeBfm : OpCodeAlu
{ {
public long WMask { get; private set; } public long WMask { get; private set; }
public long TMask { get; private set; } public long TMask { get; private set; }
public int Pos { get; private set; } public int Pos { get; private set; }
public int Shift { get; private set; } public int Shift { get; private set; }
public AOpCodeBfm(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeBfm(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
var bm = ADecoderHelper.DecodeBitMask(opCode, false); var bm = DecoderHelper.DecodeBitMask(opCode, false);
if (bm.IsUndefined) if (bm.IsUndefined)
{ {
Emitter = AInstEmit.Und; Emitter = InstEmit.Und;
return; return;
} }

10
ChocolArm64/Decoder/AOpCodeCcmp.cs → ChocolArm64/Decoder/OpCodeCcmp.cs
View file

@ -3,26 +3,26 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeCcmp : AOpCodeAlu, IaOpCodeCond class OpCodeCcmp : OpCodeAlu, IOpCodeCond
{ {
public int Nzcv { get; private set; } public int Nzcv { get; private set; }
protected int RmImm; protected int RmImm;
public ACond Cond { get; private set; } public Cond Cond { get; private set; }
public AOpCodeCcmp(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeCcmp(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
int o3 = (opCode >> 4) & 1; int o3 = (opCode >> 4) & 1;
if (o3 != 0) if (o3 != 0)
{ {
Emitter = AInstEmit.Und; Emitter = InstEmit.Und;
return; return;
} }
Nzcv = (opCode >> 0) & 0xf; Nzcv = (opCode >> 0) & 0xf;
Cond = (ACond)((opCode >> 12) & 0xf); Cond = (Cond)((opCode >> 12) & 0xf);
RmImm = (opCode >> 16) & 0x1f; RmImm = (opCode >> 16) & 0x1f;
Rd = AThreadState.ZrIndex; Rd = AThreadState.ZrIndex;

11
ChocolArm64/Decoder/OpCodeCcmpImm.cs Normal file
View file

@ -0,0 +1,11 @@
using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class OpCodeCcmpImm : OpCodeCcmp, IOpCodeAluImm
{
public long Imm => RmImm;
public OpCodeCcmpImm(Inst inst, long position, int opCode) : base(inst, position, opCode) { }
}
}

15
ChocolArm64/Decoder/OpCodeCcmpReg.cs Normal file
View file

@ -0,0 +1,15 @@
using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class OpCodeCcmpReg : OpCodeCcmp, IOpCodeAluRs
{
public int Rm => RmImm;
public int Shift => 0;
public ShiftType ShiftType => ShiftType.Lsl;
public OpCodeCcmpReg(Inst inst, long position, int opCode) : base(inst, position, opCode) { }
}
}

17
ChocolArm64/Decoder/OpCodeCsel.cs Normal file
View file

@ -0,0 +1,17 @@
using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class OpCodeCsel : OpCodeAlu, IOpCodeCond
{
public int Rm { get; private set; }
public Cond Cond { get; private set; }
public OpCodeCsel(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Rm = (opCode >> 16) & 0x1f;
Cond = (Cond)((opCode >> 12) & 0xf);
}
}
}

4
ChocolArm64/Decoder/AOpCodeException.cs → ChocolArm64/Decoder/OpCodeException.cs
View file

@ -2,11 +2,11 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeException : AOpCode class OpCodeException : AOpCode
{ {
public int Id { get; private set; } public int Id { get; private set; }
public AOpCodeException(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeException(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Id = (opCode >> 5) & 0xffff; Id = (opCode >> 5) & 0xffff;
} }

4
ChocolArm64/Decoder/AOpCodeMem.cs → ChocolArm64/Decoder/OpCodeMem.cs
View file

@ -2,14 +2,14 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeMem : AOpCode class OpCodeMem : AOpCode
{ {
public int Rt { get; protected set; } public int Rt { get; protected set; }
public int Rn { get; protected set; } public int Rn { get; protected set; }
public int Size { get; protected set; } public int Size { get; protected set; }
public bool Extend64 { get; protected set; } public bool Extend64 { get; protected set; }
public AOpCodeMem(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeMem(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rt = (opCode >> 0) & 0x1f; Rt = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f; Rn = (opCode >> 5) & 0x1f;

4
ChocolArm64/Decoder/AOpCodeMemEx.cs → ChocolArm64/Decoder/OpCodeMemEx.cs
View file

@ -2,12 +2,12 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeMemEx : AOpCodeMem class OpCodeMemEx : OpCodeMem
{ {
public int Rt2 { get; private set; } public int Rt2 { get; private set; }
public int Rs { get; private set; } public int Rs { get; private set; }
public AOpCodeMemEx(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeMemEx(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rt2 = (opCode >> 10) & 0x1f; Rt2 = (opCode >> 10) & 0x1f;
Rs = (opCode >> 16) & 0x1f; Rs = (opCode >> 16) & 0x1f;

4
ChocolArm64/Decoder/AOpCodeMemImm.cs → ChocolArm64/Decoder/OpCodeMemImm.cs
View file

@ -2,7 +2,7 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeMemImm : AOpCodeMem class OpCodeMemImm : OpCodeMem
{ {
public long Imm { get; protected set; } public long Imm { get; protected set; }
public bool WBack { get; protected set; } public bool WBack { get; protected set; }
@ -18,7 +18,7 @@ namespace ChocolArm64.Decoder
Unsigned Unsigned
} }
public AOpCodeMemImm(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeMemImm(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Extend64 = ((opCode >> 22) & 3) == 2; Extend64 = ((opCode >> 22) & 3) == 2;
WBack = ((opCode >> 24) & 1) == 0; WBack = ((opCode >> 24) & 1) == 0;

6
ChocolArm64/Decoder/AOpCodeMemLit.cs → ChocolArm64/Decoder/OpCodeMemLit.cs
View file

@ -2,7 +2,7 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeMemLit : AOpCode, IaOpCodeLit class OpCodeMemLit : AOpCode, IOpCodeLit
{ {
public int Rt { get; private set; } public int Rt { get; private set; }
public long Imm { get; private set; } public long Imm { get; private set; }
@ -10,11 +10,11 @@ namespace ChocolArm64.Decoder
public bool Signed { get; private set; } public bool Signed { get; private set; }
public bool Prefetch { get; private set; } public bool Prefetch { get; private set; }
public AOpCodeMemLit(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeMemLit(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rt = opCode & 0x1f; Rt = opCode & 0x1f;
Imm = position + ADecoderHelper.DecodeImmS19_2(opCode); Imm = position + DecoderHelper.DecodeImmS19_2(opCode);
switch ((opCode >> 30) & 3) switch ((opCode >> 30) & 3)
{ {

4
ChocolArm64/Decoder/AOpCodeMemPair.cs → ChocolArm64/Decoder/OpCodeMemPair.cs
View file

@ -2,11 +2,11 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeMemPair : AOpCodeMemImm class OpCodeMemPair : OpCodeMemImm
{ {
public int Rt2 { get; private set; } public int Rt2 { get; private set; }
public AOpCodeMemPair(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeMemPair(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rt2 = (opCode >> 10) & 0x1f; Rt2 = (opCode >> 10) & 0x1f;
WBack = ((opCode >> 23) & 0x1) != 0; WBack = ((opCode >> 23) & 0x1) != 0;

8
ChocolArm64/Decoder/AOpCodeMemReg.cs → ChocolArm64/Decoder/OpCodeMemReg.cs
View file

@ -2,17 +2,17 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeMemReg : AOpCodeMem class OpCodeMemReg : OpCodeMem
{ {
public bool Shift { get; private set; } public bool Shift { get; private set; }
public int Rm { get; private set; } public int Rm { get; private set; }
public AIntType IntType { get; private set; } public IntType IntType { get; private set; }
public AOpCodeMemReg(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeMemReg(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Shift = ((opCode >> 12) & 0x1) != 0; Shift = ((opCode >> 12) & 0x1) != 0;
IntType = (AIntType)((opCode >> 13) & 0x7); IntType = (IntType)((opCode >> 13) & 0x7);
Rm = (opCode >> 16) & 0x1f; Rm = (opCode >> 16) & 0x1f;
Extend64 = ((opCode >> 22) & 0x3) == 2; Extend64 = ((opCode >> 22) & 0x3) == 2;
} }

10
ChocolArm64/Decoder/AOpCodeMov.cs → ChocolArm64/Decoder/OpCodeMov.cs
View file

@ -3,20 +3,20 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeMov : AOpCode class OpCodeMov : AOpCode
{ {
public int Rd { get; private set; } public int Rd { get; private set; }
public long Imm { get; private set; } public long Imm { get; private set; }
public int Pos { get; private set; } public int Pos { get; private set; }
public AOpCodeMov(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeMov(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
int p1 = (opCode >> 22) & 1; int p1 = (opCode >> 22) & 1;
int sf = (opCode >> 31) & 1; int sf = (opCode >> 31) & 1;
if (sf == 0 && p1 != 0) if (sf == 0 && p1 != 0)
{ {
Emitter = AInstEmit.Und; Emitter = InstEmit.Und;
return; return;
} }
@ -29,8 +29,8 @@ namespace ChocolArm64.Decoder
Imm <<= Pos; Imm <<= Pos;
RegisterSize = (opCode >> 31) != 0 RegisterSize = (opCode >> 31) != 0
? ARegisterSize.Int64 ? State.RegisterSize.Int64
: ARegisterSize.Int32; : State.RegisterSize.Int32;
} }
} }
} }

4
ChocolArm64/Decoder/AOpCodeMul.cs → ChocolArm64/Decoder/OpCodeMul.cs
View file

@ -2,12 +2,12 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeMul : AOpCodeAlu class OpCodeMul : OpCodeAlu
{ {
public int Rm { get; private set; } public int Rm { get; private set; }
public int Ra { get; private set; } public int Ra { get; private set; }
public AOpCodeMul(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeMul(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Ra = (opCode >> 10) & 0x1f; Ra = (opCode >> 10) & 0x1f;
Rm = (opCode >> 16) & 0x1f; Rm = (opCode >> 16) & 0x1f;

8
ChocolArm64/Decoder/AOpCodeSimd.cs → ChocolArm64/Decoder/OpCodeSimd.cs
View file

@ -3,14 +3,14 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeSimd : AOpCode, IaOpCodeSimd class OpCodeSimd : AOpCode, IOpCodeSimd
{ {
public int Rd { get; private set; } public int Rd { get; private set; }
public int Rn { get; private set; } public int Rn { get; private set; }
public int Opc { get; private set; } public int Opc { get; private set; }
public int Size { get; protected set; } public int Size { get; protected set; }
public AOpCodeSimd(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimd(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rd = (opCode >> 0) & 0x1f; Rd = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f; Rn = (opCode >> 5) & 0x1f;
@ -18,8 +18,8 @@ namespace ChocolArm64.Decoder
Size = (opCode >> 22) & 0x3; Size = (opCode >> 22) & 0x3;
RegisterSize = ((opCode >> 30) & 1) != 0 RegisterSize = ((opCode >> 30) & 1) != 0
? ARegisterSize.Simd128 ? RegisterSize.Simd128
: ARegisterSize.Simd64; : RegisterSize.Simd64;
} }
} }
} }

8
ChocolArm64/Decoder/AOpCodeSimdCvt.cs → ChocolArm64/Decoder/OpCodeSimdCvt.cs
View file

@ -3,11 +3,11 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeSimdCvt : AOpCodeSimd class OpCodeSimdCvt : OpCodeSimd
{ {
public int FBits { get; private set; } public int FBits { get; private set; }
public AOpCodeSimdCvt(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdCvt(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
//TODO: //TODO:
//Und of Fixed Point variants. //Und of Fixed Point variants.
@ -24,8 +24,8 @@ namespace ChocolArm64.Decoder
FBits = 64 - scale; FBits = 64 - scale;
RegisterSize = sf != 0 RegisterSize = sf != 0
? ARegisterSize.Int64 ? State.RegisterSize.Int64
: ARegisterSize.Int32; : State.RegisterSize.Int32;
} }
} }
} }

4
ChocolArm64/Decoder/AOpCodeSimdExt.cs → ChocolArm64/Decoder/OpCodeSimdExt.cs
View file

@ -2,11 +2,11 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeSimdExt : AOpCodeSimdReg class OpCodeSimdExt : OpCodeSimdReg
{ {
public int Imm4 { get; private set; } public int Imm4 { get; private set; }
public AOpCodeSimdExt(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdExt(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Imm4 = (opCode >> 11) & 0xf; Imm4 = (opCode >> 11) & 0xf;
} }

17
ChocolArm64/Decoder/OpCodeSimdFcond.cs Normal file
View file

@ -0,0 +1,17 @@
using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class OpCodeSimdFcond : OpCodeSimdReg, IOpCodeCond
{
public int Nzcv { get; private set; }
public Cond Cond { get; private set; }
public OpCodeSimdFcond(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Nzcv = (opCode >> 0) & 0xf;
Cond = (Cond)((opCode >> 12) & 0xf);
}
}
}

8
ChocolArm64/Decoder/AOpCodeSimdFmov.cs → ChocolArm64/Decoder/OpCodeSimdFmov.cs
View file

@ -2,20 +2,20 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeSimdFmov : AOpCode, IaOpCodeSimd class OpCodeSimdFmov : AOpCode, IOpCodeSimd
{ {
public int Rd { get; private set; } public int Rd { get; private set; }
public long Imm { get; private set; } public long Imm { get; private set; }
public int Size { get; private set; } public int Size { get; private set; }
public AOpCodeSimdFmov(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdFmov(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
int imm5 = (opCode >> 5) & 0x1f; int imm5 = (opCode >> 5) & 0x1f;
int type = (opCode >> 22) & 0x3; int type = (opCode >> 22) & 0x3;
if (imm5 != 0b00000 || type > 1) if (imm5 != 0b00000 || type > 1)
{ {
Emitter = AInstEmit.Und; Emitter = InstEmit.Und;
return; return;
} }
@ -27,7 +27,7 @@ namespace ChocolArm64.Decoder
Rd = (opCode >> 0) & 0x1f; Rd = (opCode >> 0) & 0x1f;
imm = (opCode >> 13) & 0xff; imm = (opCode >> 13) & 0xff;
Imm = ADecoderHelper.DecodeImm8Float(imm, type); Imm = DecoderHelper.DecodeImm8Float(imm, type);
} }
} }
} }

10
ChocolArm64/Decoder/AOpCodeSimdImm.cs → ChocolArm64/Decoder/OpCodeSimdImm.cs
View file

@ -3,13 +3,13 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeSimdImm : AOpCode, IaOpCodeSimd class OpCodeSimdImm : AOpCode, IOpCodeSimd
{ {
public int Rd { get; private set; } public int Rd { get; private set; }
public long Imm { get; private set; } public long Imm { get; private set; }
public int Size { get; private set; } public int Size { get; private set; }
public AOpCodeSimdImm(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdImm(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rd = opCode & 0x1f; Rd = opCode & 0x1f;
@ -54,7 +54,7 @@ namespace ChocolArm64.Decoder
case 2: case 2:
case 3: case 3:
//Floating point Immediate. //Floating point Immediate.
imm = ADecoderHelper.DecodeImm8Float(imm, Size); imm = DecoderHelper.DecodeImm8Float(imm, Size);
break; break;
} }
} }
@ -82,8 +82,8 @@ namespace ChocolArm64.Decoder
Imm = imm; Imm = imm;
RegisterSize = ((opCode >> 30) & 1) != 0 RegisterSize = ((opCode >> 30) & 1) != 0
? ARegisterSize.Simd128 ? State.RegisterSize.Simd128
: ARegisterSize.Simd64; : State.RegisterSize.Simd64;
} }
private static long ShlOnes(long value, int shift) private static long ShlOnes(long value, int shift)

6
ChocolArm64/Decoder/AOpCodeSimdIns.cs → ChocolArm64/Decoder/OpCodeSimdIns.cs
View file

@ -2,19 +2,19 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeSimdIns : AOpCodeSimd class OpCodeSimdIns : OpCodeSimd
{ {
public int SrcIndex { get; private set; } public int SrcIndex { get; private set; }
public int DstIndex { get; private set; } public int DstIndex { get; private set; }
public AOpCodeSimdIns(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdIns(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
int imm4 = (opCode >> 11) & 0xf; int imm4 = (opCode >> 11) & 0xf;
int imm5 = (opCode >> 16) & 0x1f; int imm5 = (opCode >> 16) & 0x1f;
if (imm5 == 0b10000) if (imm5 == 0b10000)
{ {
Emitter = AInstEmit.Und; Emitter = InstEmit.Und;
return; return;
} }

4
ChocolArm64/Decoder/AOpCodeSimdMemImm.cs → ChocolArm64/Decoder/OpCodeSimdMemImm.cs
View file

@ -2,9 +2,9 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeSimdMemImm : AOpCodeMemImm, IaOpCodeSimd class OpCodeSimdMemImm : OpCodeMemImm, IOpCodeSimd
{ {
public AOpCodeSimdMemImm(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdMemImm(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Size |= (opCode >> 21) & 4; Size |= (opCode >> 21) & 4;

8
ChocolArm64/Decoder/AOpCodeSimdMemLit.cs → ChocolArm64/Decoder/OpCodeSimdMemLit.cs
View file

@ -2,7 +2,7 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeSimdMemLit : AOpCode, IaOpCodeSimd, IaOpCodeLit class OpCodeSimdMemLit : AOpCode, IOpCodeSimd, IOpCodeLit
{ {
public int Rt { get; private set; } public int Rt { get; private set; }
public long Imm { get; private set; } public long Imm { get; private set; }
@ -10,20 +10,20 @@ namespace ChocolArm64.Decoder
public bool Signed => false; public bool Signed => false;
public bool Prefetch => false; public bool Prefetch => false;
public AOpCodeSimdMemLit(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdMemLit(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
int opc = (opCode >> 30) & 3; int opc = (opCode >> 30) & 3;
if (opc == 3) if (opc == 3)
{ {
Emitter = AInstEmit.Und; Emitter = InstEmit.Und;
return; return;
} }
Rt = opCode & 0x1f; Rt = opCode & 0x1f;
Imm = position + ADecoderHelper.DecodeImmS19_2(opCode); Imm = position + DecoderHelper.DecodeImmS19_2(opCode);
Size = opc + 2; Size = opc + 2;
} }

12
ChocolArm64/Decoder/AOpCodeSimdMemMs.cs → ChocolArm64/Decoder/OpCodeSimdMemMs.cs
View file

@ -3,14 +3,14 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeSimdMemMs : AOpCodeMemReg, IaOpCodeSimd class OpCodeSimdMemMs : OpCodeMemReg, IOpCodeSimd
{ {
public int Reps { get; private set; } public int Reps { get; private set; }
public int SElems { get; private set; } public int SElems { get; private set; }
public int Elems { get; private set; } public int Elems { get; private set; }
public bool WBack { get; private set; } public bool WBack { get; private set; }
public AOpCodeSimdMemMs(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdMemMs(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
switch ((opCode >> 12) & 0xf) switch ((opCode >> 12) & 0xf)
{ {
@ -22,7 +22,7 @@ namespace ChocolArm64.Decoder
case 0b1000: Reps = 1; SElems = 2; break; case 0b1000: Reps = 1; SElems = 2; break;
case 0b1010: Reps = 2; SElems = 1; break; case 0b1010: Reps = 2; SElems = 1; break;
default: inst = AInst.Undefined; return; default: inst = Inst.Undefined; return;
} }
Size = (opCode >> 10) & 3; Size = (opCode >> 10) & 3;
@ -32,7 +32,7 @@ namespace ChocolArm64.Decoder
if (!q && Size == 3 && SElems != 1) if (!q && Size == 3 && SElems != 1)
{ {
inst = AInst.Undefined; inst = Inst.Undefined;
return; return;
} }
@ -40,8 +40,8 @@ namespace ChocolArm64.Decoder
Extend64 = false; Extend64 = false;
RegisterSize = q RegisterSize = q
? ARegisterSize.Simd128 ? State.RegisterSize.Simd128
: ARegisterSize.Simd64; : State.RegisterSize.Simd64;
Elems = (GetBitsCount() >> 3) >> Size; Elems = (GetBitsCount() >> 3) >> Size;
} }

4
ChocolArm64/Decoder/AOpCodeSimdMemPair.cs → ChocolArm64/Decoder/OpCodeSimdMemPair.cs
View file

@ -2,9 +2,9 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeSimdMemPair : AOpCodeMemPair, IaOpCodeSimd class OpCodeSimdMemPair : OpCodeMemPair, IOpCodeSimd
{ {
public AOpCodeSimdMemPair(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdMemPair(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Size = ((opCode >> 30) & 3) + 2; Size = ((opCode >> 30) & 3) + 2;

4
ChocolArm64/Decoder/AOpCodeSimdMemReg.cs → ChocolArm64/Decoder/OpCodeSimdMemReg.cs
View file

@ -2,9 +2,9 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeSimdMemReg : AOpCodeMemReg, IaOpCodeSimd class OpCodeSimdMemReg : OpCodeMemReg, IOpCodeSimd
{ {
public AOpCodeSimdMemReg(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdMemReg(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Size |= (opCode >> 21) & 4; Size |= (opCode >> 21) & 4;

14
ChocolArm64/Decoder/AOpCodeSimdMemSs.cs → ChocolArm64/Decoder/OpCodeSimdMemSs.cs
View file

@ -3,14 +3,14 @@ using ChocolArm64.State;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeSimdMemSs : AOpCodeMemReg, IaOpCodeSimd class OpCodeSimdMemSs : OpCodeMemReg, IOpCodeSimd
{ {
public int SElems { get; private set; } public int SElems { get; private set; }
public int Index { get; private set; } public int Index { get; private set; }
public bool Replicate { get; private set; } public bool Replicate { get; private set; }
public bool WBack { get; private set; } public bool WBack { get; private set; }
public AOpCodeSimdMemSs(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdMemSs(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
int size = (opCode >> 10) & 3; int size = (opCode >> 10) & 3;
int s = (opCode >> 12) & 1; int s = (opCode >> 12) & 1;
@ -31,7 +31,7 @@ namespace ChocolArm64.Decoder
{ {
if ((size & 1) != 0) if ((size & 1) != 0)
{ {
inst = AInst.Undefined; inst = Inst.Undefined;
return; return;
} }
@ -46,7 +46,7 @@ namespace ChocolArm64.Decoder
if ((size & 2) != 0 || if ((size & 2) != 0 ||
((size & 1) != 0 && s != 0)) ((size & 1) != 0 && s != 0))
{ {
inst = AInst.Undefined; inst = Inst.Undefined;
return; return;
} }
@ -69,7 +69,7 @@ namespace ChocolArm64.Decoder
{ {
if (l == 0 || s != 0) if (l == 0 || s != 0)
{ {
inst = AInst.Undefined; inst = Inst.Undefined;
return; return;
} }
@ -91,8 +91,8 @@ namespace ChocolArm64.Decoder
WBack = ((opCode >> 23) & 1) != 0; WBack = ((opCode >> 23) & 1) != 0;
RegisterSize = q != 0 RegisterSize = q != 0
? ARegisterSize.Simd128 ? State.RegisterSize.Simd128
: ARegisterSize.Simd64; : State.RegisterSize.Simd64;
} }
} }
} }

4
ChocolArm64/Decoder/AOpCodeSimdReg.cs → ChocolArm64/Decoder/OpCodeSimdReg.cs
View file

@ -2,13 +2,13 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeSimdReg : AOpCodeSimd class OpCodeSimdReg : OpCodeSimd
{ {
public bool Bit3 { get; private set; } public bool Bit3 { get; private set; }
public int Ra { get; private set; } public int Ra { get; private set; }
public int Rm { get; protected set; } public int Rm { get; protected set; }
public AOpCodeSimdReg(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdReg(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Bit3 = ((opCode >> 3) & 0x1) != 0; Bit3 = ((opCode >> 3) & 0x1) != 0;
Ra = (opCode >> 10) & 0x1f; Ra = (opCode >> 10) & 0x1f;

6
ChocolArm64/Decoder/AOpCodeSimdRegElem.cs → ChocolArm64/Decoder/OpCodeSimdRegElem.cs
View file

@ -2,11 +2,11 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeSimdRegElem : AOpCodeSimdReg class OpCodeSimdRegElem : OpCodeSimdReg
{ {
public int Index { get; private set; } public int Index { get; private set; }
public AOpCodeSimdRegElem(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdRegElem(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
switch (Size) switch (Size)
{ {
@ -24,7 +24,7 @@ namespace ChocolArm64.Decoder
break; break;
default: Emitter = AInstEmit.Und; return; default: Emitter = InstEmit.Und; return;
} }
} }
} }

6
ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs → ChocolArm64/Decoder/OpCodeSimdRegElemF.cs
View file

@ -2,11 +2,11 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeSimdRegElemF : AOpCodeSimdReg class OpCodeSimdRegElemF : OpCodeSimdReg
{ {
public int Index { get; private set; } public int Index { get; private set; }
public AOpCodeSimdRegElemF(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdRegElemF(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
switch ((opCode >> 21) & 3) // sz:L switch ((opCode >> 21) & 3) // sz:L
{ {
@ -26,7 +26,7 @@ namespace ChocolArm64.Decoder
break; break;
default: Emitter = AInstEmit.Und; return; default: Emitter = InstEmit.Und; return;
} }
} }
} }

16
ChocolArm64/Decoder/OpCodeSimdShImm.cs Normal file
View file

@ -0,0 +1,16 @@
using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class OpCodeSimdShImm : OpCodeSimd
{
public int Imm { get; private set; }
public OpCodeSimdShImm(Inst inst, long position, int opCode) : base(inst, position, opCode)
{
Imm = (opCode >> 16) & 0x7f;
Size = BitUtils.HighestBitSetNibble(Imm >> 3);
}
}
}

4
ChocolArm64/Decoder/AOpCodeSimdTbl.cs → ChocolArm64/Decoder/OpCodeSimdTbl.cs
View file

@ -2,9 +2,9 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeSimdTbl : AOpCodeSimdReg class OpCodeSimdTbl : OpCodeSimdReg
{ {
public AOpCodeSimdTbl(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSimdTbl(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Size = ((opCode >> 13) & 3) + 1; Size = ((opCode >> 13) & 3) + 1;
} }

4
ChocolArm64/Decoder/AOpCodeSystem.cs → ChocolArm64/Decoder/OpCodeSystem.cs
View file

@ -2,7 +2,7 @@ using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
class AOpCodeSystem : AOpCode class OpCodeSystem : AOpCode
{ {
public int Rt { get; private set; } public int Rt { get; private set; }
public int Op2 { get; private set; } public int Op2 { get; private set; }
@ -11,7 +11,7 @@ namespace ChocolArm64.Decoder
public int Op1 { get; private set; } public int Op1 { get; private set; }
public int Op0 { get; private set; } public int Op0 { get; private set; }
public AOpCodeSystem(AInst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeSystem(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rt = (opCode >> 0) & 0x1f; Rt = (opCode >> 0) & 0x1f;
Op2 = (opCode >> 5) & 0x7; Op2 = (opCode >> 5) & 0x7;

2
ChocolArm64/Decoder/AShiftType.cs → ChocolArm64/Decoder/ShiftType.cs
View file

@ -1,6 +1,6 @@
namespace ChocolArm64.Decoder namespace ChocolArm64.Decoder
{ {
enum AShiftType enum ShiftType
{ {
Lsl, Lsl,
Lsr, Lsr,

6
ChocolArm64/Decoder32/A32OpCode.cs
View file

@ -5,11 +5,11 @@ namespace ChocolArm64.Decoder32
{ {
class A32OpCode : AOpCode class A32OpCode : AOpCode
{ {
public ACond Cond { get; private set; } public Cond Cond { get; private set; }
public A32OpCode(AInst inst, long position, int opCode) : base(inst, position, opCode) public A32OpCode(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Cond = (ACond)((uint)opCode >> 28); Cond = (Cond)((uint)opCode >> 28);
} }
} }
} }

2
ChocolArm64/Decoder32/A32OpCodeBImmAl.cs
View file

@ -7,7 +7,7 @@ namespace ChocolArm64.Decoder32
public int Imm; public int Imm;
public int H; public int H;
public A32OpCodeBImmAl(AInst inst, long position, int opCode) : base(inst, position, opCode) public A32OpCodeBImmAl(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Imm = (opCode << 8) >> 6; Imm = (opCode << 8) >> 6;
H = (opCode >> 23) & 2; H = (opCode >> 23) & 2;

4
ChocolArm64/Events/ACpuTraceEventArgs.cs → ChocolArm64/Events/CpuTraceEventArgs.cs
View file

@ -2,11 +2,11 @@ using System;
namespace ChocolArm64.Events namespace ChocolArm64.Events
{ {
public class ACpuTraceEventArgs : EventArgs public class CpuTraceEventArgs : EventArgs
{ {
public long Position { get; private set; } public long Position { get; private set; }
public ACpuTraceEventArgs(long position) public CpuTraceEventArgs(long position)
{ {
Position = position; Position = position;
} }

4
ChocolArm64/Events/AInstExceptionEventArgs.cs → ChocolArm64/Events/InstExceptionEventArgs.cs
View file

@ -2,12 +2,12 @@ using System;
namespace ChocolArm64.Events namespace ChocolArm64.Events
{ {
public class AInstExceptionEventArgs : EventArgs public class InstExceptionEventArgs : EventArgs
{ {
public long Position { get; private set; } public long Position { get; private set; }
public int Id { get; private set; } public int Id { get; private set; }
public AInstExceptionEventArgs(long position, int id) public InstExceptionEventArgs(long position, int id)
{ {
Position = position; Position = position;
Id = id; Id = id;

4
ChocolArm64/Events/AInstUndefinedEventArgs.cs → ChocolArm64/Events/InstUndefinedEventArgs.cs
View file

@ -2,12 +2,12 @@ using System;
namespace ChocolArm64.Events namespace ChocolArm64.Events
{ {
public class AInstUndefinedEventArgs : EventArgs public class InstUndefinedEventArgs : EventArgs
{ {
public long Position { get; private set; } public long Position { get; private set; }
public int RawOpCode { get; private set; } public int RawOpCode { get; private set; }
public AInstUndefinedEventArgs(long position, int rawOpCode) public InstUndefinedEventArgs(long position, int rawOpCode)
{ {
Position = position; Position = position;
RawOpCode = rawOpCode; RawOpCode = rawOpCode;

4
ChocolArm64/Events/AInvalidAccessEventArgs.cs → ChocolArm64/Events/InvalidAccessEventArgs.cs
View file

@ -2,11 +2,11 @@ using System;
namespace ChocolArm64.Events namespace ChocolArm64.Events
{ {
public class AInvalidAccessEventArgs : EventArgs public class InvalidAccessEventArgs : EventArgs
{ {
public long Position { get; private set; } public long Position { get; private set; }
public AInvalidAccessEventArgs(long position) public InvalidAccessEventArgs(long position)
{ {
Position = position; Position = position;
} }

20
ChocolArm64/Instruction/AInst.cs
View file

@ -1,20 +0,0 @@
using System;
namespace ChocolArm64.Instruction
{
struct AInst
{
public AInstInterpreter Interpreter { get; private set; }
public AInstEmitter Emitter { get; private set; }
public Type Type { get; private set; }
public static AInst Undefined => new AInst(null, AInstEmit.Und, null);
public AInst(AInstInterpreter interpreter, AInstEmitter emitter, Type type)
{
Interpreter = interpreter;
Emitter = emitter;
Type = type;
}
}
}

115
ChocolArm64/Instruction/AInstEmitHash.cs
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@ -1,115 +0,0 @@
using ChocolArm64.Decoder;
using ChocolArm64.State;
using ChocolArm64.Translation;
using System;
using System.Reflection.Emit;
using System.Runtime.Intrinsics.X86;
namespace ChocolArm64.Instruction
{
static partial class AInstEmit
{
public static void Crc32b(AilEmitterCtx context)
{
EmitCrc32(context, nameof(ASoftFallback.Crc32B));
}
public static void Crc32h(AilEmitterCtx context)
{
EmitCrc32(context, nameof(ASoftFallback.Crc32H));
}
public static void Crc32w(AilEmitterCtx context)
{
EmitCrc32(context, nameof(ASoftFallback.Crc32W));
}
public static void Crc32x(AilEmitterCtx context)
{
EmitCrc32(context, nameof(ASoftFallback.Crc32X));
}
public static void Crc32cb(AilEmitterCtx context)
{
if (AOptimizations.UseSse42)
{
EmitSse42Crc32(context, typeof(uint), typeof(byte));
}
else
{
EmitCrc32(context, nameof(ASoftFallback.Crc32Cb));
}
}
public static void Crc32ch(AilEmitterCtx context)
{
if (AOptimizations.UseSse42)
{
EmitSse42Crc32(context, typeof(uint), typeof(ushort));
}
else
{
EmitCrc32(context, nameof(ASoftFallback.Crc32Ch));
}
}
public static void Crc32cw(AilEmitterCtx context)
{
if (AOptimizations.UseSse42)
{
EmitSse42Crc32(context, typeof(uint), typeof(uint));
}
else
{
EmitCrc32(context, nameof(ASoftFallback.Crc32Cw));
}
}
public static void Crc32cx(AilEmitterCtx context)
{
if (AOptimizations.UseSse42)
{
EmitSse42Crc32(context, typeof(ulong), typeof(ulong));
}
else
{
EmitCrc32(context, nameof(ASoftFallback.Crc32Cx));
}
}
private static void EmitSse42Crc32(AilEmitterCtx context, Type tCrc, Type tData)
{
AOpCodeAluRs op = (AOpCodeAluRs)context.CurrOp;
context.EmitLdintzr(op.Rn);
context.EmitLdintzr(op.Rm);
context.EmitCall(typeof(Sse42).GetMethod(nameof(Sse42.Crc32), new Type[] { tCrc, tData }));
context.EmitStintzr(op.Rd);
}
private static void EmitCrc32(AilEmitterCtx context, string name)
{
AOpCodeAluRs op = (AOpCodeAluRs)context.CurrOp;
context.EmitLdintzr(op.Rn);
if (op.RegisterSize != ARegisterSize.Int32)
{
context.Emit(OpCodes.Conv_U4);
}
context.EmitLdintzr(op.Rm);
ASoftFallback.EmitCall(context, name);
if (op.RegisterSize != ARegisterSize.Int32)
{
context.Emit(OpCodes.Conv_U8);
}
context.EmitStintzr(op.Rd);
}
}
}

80
ChocolArm64/Instruction/AInstEmitMul.cs
View file

@ -1,80 +0,0 @@
using ChocolArm64.Decoder;
using ChocolArm64.Translation;
using System.Reflection.Emit;
namespace ChocolArm64.Instruction
{
static partial class AInstEmit
{
public static void Madd(AilEmitterCtx context) => EmitMul(context, OpCodes.Add);
public static void Msub(AilEmitterCtx context) => EmitMul(context, OpCodes.Sub);
private static void EmitMul(AilEmitterCtx context, OpCode ilOp)
{
AOpCodeMul op = (AOpCodeMul)context.CurrOp;
context.EmitLdintzr(op.Ra);
context.EmitLdintzr(op.Rn);
context.EmitLdintzr(op.Rm);
context.Emit(OpCodes.Mul);
context.Emit(ilOp);
context.EmitStintzr(op.Rd);
}
public static void Smaddl(AilEmitterCtx context) => EmitMull(context, OpCodes.Add, true);
public static void Smsubl(AilEmitterCtx context) => EmitMull(context, OpCodes.Sub, true);
public static void Umaddl(AilEmitterCtx context) => EmitMull(context, OpCodes.Add, false);
public static void Umsubl(AilEmitterCtx context) => EmitMull(context, OpCodes.Sub, false);
private static void EmitMull(AilEmitterCtx context, OpCode addSubOp, bool signed)
{
AOpCodeMul op = (AOpCodeMul)context.CurrOp;
OpCode castOp = signed
? OpCodes.Conv_I8
: OpCodes.Conv_U8;
context.EmitLdintzr(op.Ra);
context.EmitLdintzr(op.Rn);
context.Emit(OpCodes.Conv_I4);
context.Emit(castOp);
context.EmitLdintzr(op.Rm);
context.Emit(OpCodes.Conv_I4);
context.Emit(castOp);
context.Emit(OpCodes.Mul);
context.Emit(addSubOp);
context.EmitStintzr(op.Rd);
}
public static void Smulh(AilEmitterCtx context)
{
AOpCodeMul op = (AOpCodeMul)context.CurrOp;
context.EmitLdintzr(op.Rn);
context.EmitLdintzr(op.Rm);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.SMulHi128));
context.EmitStintzr(op.Rd);
}
public static void Umulh(AilEmitterCtx context)
{
AOpCodeMul op = (AOpCodeMul)context.CurrOp;
context.EmitLdintzr(op.Rn);
context.EmitLdintzr(op.Rm);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.UMulHi128));
context.EmitStintzr(op.Rd);
}
}
}

54
ChocolArm64/Instruction/AInstEmitSimdCrypto.cs
View file

@ -1,54 +0,0 @@
using ChocolArm64.Decoder;
using ChocolArm64.Translation;
namespace ChocolArm64.Instruction
{
static partial class AInstEmit
{
public static void Aesd_V(AilEmitterCtx context)
{
AOpCodeSimd op = (AOpCodeSimd)context.CurrOp;
context.EmitLdvec(op.Rd);
context.EmitLdvec(op.Rn);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.Decrypt));
context.EmitStvec(op.Rd);
}
public static void Aese_V(AilEmitterCtx context)
{
AOpCodeSimd op = (AOpCodeSimd)context.CurrOp;
context.EmitLdvec(op.Rd);
context.EmitLdvec(op.Rn);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.Encrypt));
context.EmitStvec(op.Rd);
}
public static void Aesimc_V(AilEmitterCtx context)
{
AOpCodeSimd op = (AOpCodeSimd)context.CurrOp;
context.EmitLdvec(op.Rn);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.InverseMixColumns));
context.EmitStvec(op.Rd);
}
public static void Aesmc_V(AilEmitterCtx context)
{
AOpCodeSimd op = (AOpCodeSimd)context.CurrOp;
context.EmitLdvec(op.Rn);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.MixColumns));
context.EmitStvec(op.Rd);
}
}
}

140
ChocolArm64/Instruction/AInstEmitSimdHash.cs
View file

@ -1,140 +0,0 @@
using ChocolArm64.Decoder;
using ChocolArm64.Translation;
using static ChocolArm64.Instruction.AInstEmitSimdHelper;
namespace ChocolArm64.Instruction
{
static partial class AInstEmit
{
#region "Sha1"
public static void Sha1c_V(AilEmitterCtx context)
{
AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp;
context.EmitLdvec(op.Rd);
EmitVectorExtractZx(context, op.Rn, 0, 2);
context.EmitLdvec(op.Rm);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.HashChoose));
context.EmitStvec(op.Rd);
}
public static void Sha1h_V(AilEmitterCtx context)
{
AOpCodeSimd op = (AOpCodeSimd)context.CurrOp;
EmitVectorExtractZx(context, op.Rn, 0, 2);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.FixedRotate));
EmitScalarSet(context, op.Rd, 2);
}
public static void Sha1m_V(AilEmitterCtx context)
{
AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp;
context.EmitLdvec(op.Rd);
EmitVectorExtractZx(context, op.Rn, 0, 2);
context.EmitLdvec(op.Rm);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.HashMajority));
context.EmitStvec(op.Rd);
}
public static void Sha1p_V(AilEmitterCtx context)
{
AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp;
context.EmitLdvec(op.Rd);
EmitVectorExtractZx(context, op.Rn, 0, 2);
context.EmitLdvec(op.Rm);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.HashParity));
context.EmitStvec(op.Rd);
}
public static void Sha1su0_V(AilEmitterCtx context)
{
AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp;
context.EmitLdvec(op.Rd);
context.EmitLdvec(op.Rn);
context.EmitLdvec(op.Rm);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.Sha1SchedulePart1));
context.EmitStvec(op.Rd);
}
public static void Sha1su1_V(AilEmitterCtx context)
{
AOpCodeSimd op = (AOpCodeSimd)context.CurrOp;
context.EmitLdvec(op.Rd);
context.EmitLdvec(op.Rn);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.Sha1SchedulePart2));
context.EmitStvec(op.Rd);
}
#endregion
#region "Sha256"
public static void Sha256h_V(AilEmitterCtx context)
{
AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp;
context.EmitLdvec(op.Rd);
context.EmitLdvec(op.Rn);
context.EmitLdvec(op.Rm);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.HashLower));
context.EmitStvec(op.Rd);
}
public static void Sha256h2_V(AilEmitterCtx context)
{
AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp;
context.EmitLdvec(op.Rd);
context.EmitLdvec(op.Rn);
context.EmitLdvec(op.Rm);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.HashUpper));
context.EmitStvec(op.Rd);
}
public static void Sha256su0_V(AilEmitterCtx context)
{
AOpCodeSimd op = (AOpCodeSimd)context.CurrOp;
context.EmitLdvec(op.Rd);
context.EmitLdvec(op.Rn);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.Sha256SchedulePart1));
context.EmitStvec(op.Rd);
}
public static void Sha256su1_V(AilEmitterCtx context)
{
AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp;
context.EmitLdvec(op.Rd);
context.EmitLdvec(op.Rn);
context.EmitLdvec(op.Rm);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.Sha256SchedulePart2));
context.EmitStvec(op.Rd);
}
#endregion
}
}

6
ChocolArm64/Instruction/ACryptoHelper.cs → ChocolArm64/Instruction/CryptoHelper.cs
View file

@ -6,7 +6,7 @@ using System.Runtime.Intrinsics.X86;
namespace ChocolArm64.Instruction namespace ChocolArm64.Instruction
{ {
static class ACryptoHelper static class CryptoHelper
{ {
#region "LookUp Tables" #region "LookUp Tables"
private static byte[] _sBox = private static byte[] _sBox =
@ -298,8 +298,8 @@ namespace ChocolArm64.Instruction
private static void FromVectorToByteArray(byte[] state, ref Vector128<float> op) private static void FromVectorToByteArray(byte[] state, ref Vector128<float> op)
{ {
ulong uLongLow = AVectorHelper.VectorExtractIntZx((op), (byte)0, 3); ulong uLongLow = VectorHelper.VectorExtractIntZx((op), (byte)0, 3);
ulong uLongHigh = AVectorHelper.VectorExtractIntZx((op), (byte)1, 3); ulong uLongHigh = VectorHelper.VectorExtractIntZx((op), (byte)1, 3);
for (int idx = 0; idx <= 7; idx++) for (int idx = 0; idx <= 7; idx++)
{ {

20
ChocolArm64/Instruction/Inst.cs Normal file
View file

@ -0,0 +1,20 @@
using System;
namespace ChocolArm64.Instruction
{
struct Inst
{
public InstInterpreter Interpreter { get; private set; }
public InstEmitter Emitter { get; private set; }
public Type Type { get; private set; }
public static Inst Undefined => new Inst(null, InstEmit.Und, null);
public Inst(InstInterpreter interpreter, InstEmitter emitter, Type type)
{
Interpreter = interpreter;
Emitter = emitter;
Type = type;
}
}
}

136
ChocolArm64/Instruction/AInstEmitAlu.cs → ChocolArm64/Instruction/InstEmitAlu.cs
View file

@ -6,22 +6,22 @@ using System.Reflection;
using System.Reflection.Emit; using System.Reflection.Emit;
using System.Runtime.Intrinsics.X86; using System.Runtime.Intrinsics.X86;
using static ChocolArm64.Instruction.AInstEmitAluHelper; using static ChocolArm64.Instruction.InstEmitAluHelper;
namespace ChocolArm64.Instruction namespace ChocolArm64.Instruction
{ {
static partial class AInstEmit static partial class InstEmit
{ {
public static void Adc(AilEmitterCtx context) => EmitAdc(context, false); public static void Adc(ILEmitterCtx context) => EmitAdc(context, false);
public static void Adcs(AilEmitterCtx context) => EmitAdc(context, true); public static void Adcs(ILEmitterCtx context) => EmitAdc(context, true);
private static void EmitAdc(AilEmitterCtx context, bool setFlags) private static void EmitAdc(ILEmitterCtx context, bool setFlags)
{ {
EmitDataLoadOpers(context); EmitDataLoadOpers(context);
context.Emit(OpCodes.Add); context.Emit(OpCodes.Add);
context.EmitLdflg((int)ApState.CBit); context.EmitLdflg((int)PState.CBit);
Type[] mthdTypes = new Type[] { typeof(bool) }; Type[] mthdTypes = new Type[] { typeof(bool) };
@ -29,7 +29,7 @@ namespace ChocolArm64.Instruction
context.EmitCall(mthdInfo); context.EmitCall(mthdInfo);
if (context.CurrOp.RegisterSize != ARegisterSize.Int32) if (context.CurrOp.RegisterSize != RegisterSize.Int32)
{ {
context.Emit(OpCodes.Conv_U8); context.Emit(OpCodes.Conv_U8);
} }
@ -47,9 +47,9 @@ namespace ChocolArm64.Instruction
EmitDataStore(context); EmitDataStore(context);
} }
public static void Add(AilEmitterCtx context) => EmitDataOp(context, OpCodes.Add); public static void Add(ILEmitterCtx context) => EmitDataOp(context, OpCodes.Add);
public static void Adds(AilEmitterCtx context) public static void Adds(ILEmitterCtx context)
{ {
EmitDataLoadOpers(context); EmitDataLoadOpers(context);
@ -62,9 +62,9 @@ namespace ChocolArm64.Instruction
EmitDataStoreS(context); EmitDataStoreS(context);
} }
public static void And(AilEmitterCtx context) => EmitDataOp(context, OpCodes.And); public static void And(ILEmitterCtx context) => EmitDataOp(context, OpCodes.And);
public static void Ands(AilEmitterCtx context) public static void Ands(ILEmitterCtx context)
{ {
EmitDataLoadOpers(context); EmitDataLoadOpers(context);
@ -77,12 +77,12 @@ namespace ChocolArm64.Instruction
EmitDataStoreS(context); EmitDataStoreS(context);
} }
public static void Asrv(AilEmitterCtx context) => EmitDataOpShift(context, OpCodes.Shr); public static void Asrv(ILEmitterCtx context) => EmitDataOpShift(context, OpCodes.Shr);
public static void Bic(AilEmitterCtx context) => EmitBic(context, false); public static void Bic(ILEmitterCtx context) => EmitBic(context, false);
public static void Bics(AilEmitterCtx context) => EmitBic(context, true); public static void Bics(ILEmitterCtx context) => EmitBic(context, true);
private static void EmitBic(AilEmitterCtx context, bool setFlags) private static void EmitBic(ILEmitterCtx context, bool setFlags)
{ {
EmitDataLoadOpers(context); EmitDataLoadOpers(context);
@ -99,42 +99,42 @@ namespace ChocolArm64.Instruction
EmitDataStore(context, setFlags); EmitDataStore(context, setFlags);
} }
public static void Cls(AilEmitterCtx context) public static void Cls(ILEmitterCtx context)
{ {
AOpCodeAlu op = (AOpCodeAlu)context.CurrOp; OpCodeAlu op = (OpCodeAlu)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
context.EmitLdc_I4(op.RegisterSize == ARegisterSize.Int32 ? 32 : 64); context.EmitLdc_I4(op.RegisterSize == RegisterSize.Int32 ? 32 : 64);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.CountLeadingSigns)); SoftFallback.EmitCall(context, nameof(SoftFallback.CountLeadingSigns));
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
} }
public static void Clz(AilEmitterCtx context) public static void Clz(ILEmitterCtx context)
{ {
AOpCodeAlu op = (AOpCodeAlu)context.CurrOp; OpCodeAlu op = (OpCodeAlu)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
if (Lzcnt.IsSupported) if (Lzcnt.IsSupported)
{ {
Type tValue = op.RegisterSize == ARegisterSize.Int32 ? typeof(uint) : typeof(ulong); Type tValue = op.RegisterSize == RegisterSize.Int32 ? typeof(uint) : typeof(ulong);
context.EmitCall(typeof(Lzcnt).GetMethod(nameof(Lzcnt.LeadingZeroCount), new Type[] { tValue })); context.EmitCall(typeof(Lzcnt).GetMethod(nameof(Lzcnt.LeadingZeroCount), new Type[] { tValue }));
} }
else else
{ {
context.EmitLdc_I4(op.RegisterSize == ARegisterSize.Int32 ? 32 : 64); context.EmitLdc_I4(op.RegisterSize == RegisterSize.Int32 ? 32 : 64);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.CountLeadingZeros)); SoftFallback.EmitCall(context, nameof(SoftFallback.CountLeadingZeros));
} }
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
} }
public static void Eon(AilEmitterCtx context) public static void Eon(ILEmitterCtx context)
{ {
EmitDataLoadOpers(context); EmitDataLoadOpers(context);
@ -144,12 +144,12 @@ namespace ChocolArm64.Instruction
EmitDataStore(context); EmitDataStore(context);
} }
public static void Eor(AilEmitterCtx context) => EmitDataOp(context, OpCodes.Xor); public static void Eor(ILEmitterCtx context) => EmitDataOp(context, OpCodes.Xor);
public static void Extr(AilEmitterCtx context) public static void Extr(ILEmitterCtx context)
{ {
//TODO: Ensure that the Shift is valid for the Is64Bits. //TODO: Ensure that the Shift is valid for the Is64Bits.
AOpCodeAluRs op = (AOpCodeAluRs)context.CurrOp; OpCodeAluRs op = (OpCodeAluRs)context.CurrOp;
context.EmitLdintzr(op.Rm); context.EmitLdintzr(op.Rm);
@ -169,19 +169,19 @@ namespace ChocolArm64.Instruction
EmitDataStore(context); EmitDataStore(context);
} }
public static void Lslv(AilEmitterCtx context) => EmitDataOpShift(context, OpCodes.Shl); public static void Lslv(ILEmitterCtx context) => EmitDataOpShift(context, OpCodes.Shl);
public static void Lsrv(AilEmitterCtx context) => EmitDataOpShift(context, OpCodes.Shr_Un); public static void Lsrv(ILEmitterCtx context) => EmitDataOpShift(context, OpCodes.Shr_Un);
public static void Sbc(AilEmitterCtx context) => EmitSbc(context, false); public static void Sbc(ILEmitterCtx context) => EmitSbc(context, false);
public static void Sbcs(AilEmitterCtx context) => EmitSbc(context, true); public static void Sbcs(ILEmitterCtx context) => EmitSbc(context, true);
private static void EmitSbc(AilEmitterCtx context, bool setFlags) private static void EmitSbc(ILEmitterCtx context, bool setFlags)
{ {
EmitDataLoadOpers(context); EmitDataLoadOpers(context);
context.Emit(OpCodes.Sub); context.Emit(OpCodes.Sub);
context.EmitLdflg((int)ApState.CBit); context.EmitLdflg((int)PState.CBit);
Type[] mthdTypes = new Type[] { typeof(bool) }; Type[] mthdTypes = new Type[] { typeof(bool) };
@ -193,7 +193,7 @@ namespace ChocolArm64.Instruction
context.Emit(OpCodes.Xor); context.Emit(OpCodes.Xor);
if (context.CurrOp.RegisterSize != ARegisterSize.Int32) if (context.CurrOp.RegisterSize != RegisterSize.Int32)
{ {
context.Emit(OpCodes.Conv_U8); context.Emit(OpCodes.Conv_U8);
} }
@ -211,9 +211,9 @@ namespace ChocolArm64.Instruction
EmitDataStore(context); EmitDataStore(context);
} }
public static void Sub(AilEmitterCtx context) => EmitDataOp(context, OpCodes.Sub); public static void Sub(ILEmitterCtx context) => EmitDataOp(context, OpCodes.Sub);
public static void Subs(AilEmitterCtx context) public static void Subs(ILEmitterCtx context)
{ {
context.TryOptMarkCondWithoutCmp(); context.TryOptMarkCondWithoutCmp();
@ -228,7 +228,7 @@ namespace ChocolArm64.Instruction
EmitDataStoreS(context); EmitDataStoreS(context);
} }
public static void Orn(AilEmitterCtx context) public static void Orn(ILEmitterCtx context)
{ {
EmitDataLoadOpers(context); EmitDataLoadOpers(context);
@ -238,50 +238,50 @@ namespace ChocolArm64.Instruction
EmitDataStore(context); EmitDataStore(context);
} }
public static void Orr(AilEmitterCtx context) => EmitDataOp(context, OpCodes.Or); public static void Orr(ILEmitterCtx context) => EmitDataOp(context, OpCodes.Or);
public static void Rbit(AilEmitterCtx context) => EmitFallback32_64(context, public static void Rbit(ILEmitterCtx context) => EmitFallback32_64(context,
nameof(ASoftFallback.ReverseBits32), nameof(SoftFallback.ReverseBits32),
nameof(ASoftFallback.ReverseBits64)); nameof(SoftFallback.ReverseBits64));
public static void Rev16(AilEmitterCtx context) => EmitFallback32_64(context, public static void Rev16(ILEmitterCtx context) => EmitFallback32_64(context,
nameof(ASoftFallback.ReverseBytes16_32), nameof(SoftFallback.ReverseBytes16_32),
nameof(ASoftFallback.ReverseBytes16_64)); nameof(SoftFallback.ReverseBytes16_64));
public static void Rev32(AilEmitterCtx context) => EmitFallback32_64(context, public static void Rev32(ILEmitterCtx context) => EmitFallback32_64(context,
nameof(ASoftFallback.ReverseBytes32_32), nameof(SoftFallback.ReverseBytes32_32),
nameof(ASoftFallback.ReverseBytes32_64)); nameof(SoftFallback.ReverseBytes32_64));
private static void EmitFallback32_64(AilEmitterCtx context, string name32, string name64) private static void EmitFallback32_64(ILEmitterCtx context, string name32, string name64)
{ {
AOpCodeAlu op = (AOpCodeAlu)context.CurrOp; OpCodeAlu op = (OpCodeAlu)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
if (op.RegisterSize == ARegisterSize.Int32) if (op.RegisterSize == RegisterSize.Int32)
{ {
ASoftFallback.EmitCall(context, name32); SoftFallback.EmitCall(context, name32);
} }
else else
{ {
ASoftFallback.EmitCall(context, name64); SoftFallback.EmitCall(context, name64);
} }
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
} }
public static void Rev64(AilEmitterCtx context) public static void Rev64(ILEmitterCtx context)
{ {
AOpCodeAlu op = (AOpCodeAlu)context.CurrOp; OpCodeAlu op = (OpCodeAlu)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
ASoftFallback.EmitCall(context, nameof(ASoftFallback.ReverseBytes64)); SoftFallback.EmitCall(context, nameof(SoftFallback.ReverseBytes64));
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
} }
public static void Rorv(AilEmitterCtx context) public static void Rorv(ILEmitterCtx context)
{ {
EmitDataLoadRn(context); EmitDataLoadRn(context);
EmitDataLoadShift(context); EmitDataLoadShift(context);
@ -301,10 +301,10 @@ namespace ChocolArm64.Instruction
EmitDataStore(context); EmitDataStore(context);
} }
public static void Sdiv(AilEmitterCtx context) => EmitDiv(context, OpCodes.Div); public static void Sdiv(ILEmitterCtx context) => EmitDiv(context, OpCodes.Div);
public static void Udiv(AilEmitterCtx context) => EmitDiv(context, OpCodes.Div_Un); public static void Udiv(ILEmitterCtx context) => EmitDiv(context, OpCodes.Div_Un);
private static void EmitDiv(AilEmitterCtx context, OpCode ilOp) private static void EmitDiv(ILEmitterCtx context, OpCode ilOp)
{ {
//If Rm == 0, Rd = 0 (division by zero). //If Rm == 0, Rd = 0 (division by zero).
context.EmitLdc_I(0); context.EmitLdc_I(0);
@ -313,7 +313,7 @@ namespace ChocolArm64.Instruction
context.EmitLdc_I(0); context.EmitLdc_I(0);
AilLabel badDiv = new AilLabel(); ILLabel badDiv = new ILLabel();
context.Emit(OpCodes.Beq_S, badDiv); context.Emit(OpCodes.Beq_S, badDiv);
context.Emit(OpCodes.Pop); context.Emit(OpCodes.Pop);
@ -351,7 +351,7 @@ namespace ChocolArm64.Instruction
EmitDataStore(context); EmitDataStore(context);
} }
private static void EmitDataOp(AilEmitterCtx context, OpCode ilOp) private static void EmitDataOp(ILEmitterCtx context, OpCode ilOp)
{ {
EmitDataLoadOpers(context); EmitDataLoadOpers(context);
@ -360,7 +360,7 @@ namespace ChocolArm64.Instruction
EmitDataStore(context); EmitDataStore(context);
} }
private static void EmitDataOpShift(AilEmitterCtx context, OpCode ilOp) private static void EmitDataOpShift(ILEmitterCtx context, OpCode ilOp)
{ {
EmitDataLoadRn(context); EmitDataLoadRn(context);
EmitDataLoadShift(context); EmitDataLoadShift(context);
@ -370,7 +370,7 @@ namespace ChocolArm64.Instruction
EmitDataStore(context); EmitDataStore(context);
} }
private static void EmitDataLoadShift(AilEmitterCtx context) private static void EmitDataLoadShift(ILEmitterCtx context)
{ {
EmitDataLoadRm(context); EmitDataLoadRm(context);
@ -382,21 +382,21 @@ namespace ChocolArm64.Instruction
//we need to cast it to a 32-bits integer. This is fine because we //we need to cast it to a 32-bits integer. This is fine because we
//AND the value and only keep the lower 5 or 6 bits anyway -- it //AND the value and only keep the lower 5 or 6 bits anyway -- it
//could very well fit on a byte. //could very well fit on a byte.
if (context.CurrOp.RegisterSize != ARegisterSize.Int32) if (context.CurrOp.RegisterSize != RegisterSize.Int32)
{ {
context.Emit(OpCodes.Conv_I4); context.Emit(OpCodes.Conv_I4);
} }
} }
private static void EmitZeroCvFlags(AilEmitterCtx context) private static void EmitZeroCvFlags(ILEmitterCtx context)
{ {
context.EmitLdc_I4(0); context.EmitLdc_I4(0);
context.EmitStflg((int)ApState.VBit); context.EmitStflg((int)PState.VBit);
context.EmitLdc_I4(0); context.EmitLdc_I4(0);
context.EmitStflg((int)ApState.CBit); context.EmitStflg((int)PState.CBit);
} }
} }
} }

78
ChocolArm64/Instruction/AInstEmitAluHelper.cs → ChocolArm64/Instruction/InstEmitAluHelper.cs
View file

@ -5,9 +5,9 @@ using System.Reflection.Emit;
namespace ChocolArm64.Instruction namespace ChocolArm64.Instruction
{ {
static class AInstEmitAluHelper static class InstEmitAluHelper
{ {
public static void EmitAdcsCCheck(AilEmitterCtx context) public static void EmitAdcsCCheck(ILEmitterCtx context)
{ {
//C = (Rd == Rn && CIn) || Rd < Rn //C = (Rd == Rn && CIn) || Rd < Rn
context.EmitSttmp(); context.EmitSttmp();
@ -18,7 +18,7 @@ namespace ChocolArm64.Instruction
context.Emit(OpCodes.Ceq); context.Emit(OpCodes.Ceq);
context.EmitLdflg((int)ApState.CBit); context.EmitLdflg((int)PState.CBit);
context.Emit(OpCodes.And); context.Emit(OpCodes.And);
@ -29,10 +29,10 @@ namespace ChocolArm64.Instruction
context.Emit(OpCodes.Clt_Un); context.Emit(OpCodes.Clt_Un);
context.Emit(OpCodes.Or); context.Emit(OpCodes.Or);
context.EmitStflg((int)ApState.CBit); context.EmitStflg((int)PState.CBit);
} }
public static void EmitAddsCCheck(AilEmitterCtx context) public static void EmitAddsCCheck(ILEmitterCtx context)
{ {
//C = Rd < Rn //C = Rd < Rn
context.Emit(OpCodes.Dup); context.Emit(OpCodes.Dup);
@ -41,10 +41,10 @@ namespace ChocolArm64.Instruction
context.Emit(OpCodes.Clt_Un); context.Emit(OpCodes.Clt_Un);
context.EmitStflg((int)ApState.CBit); context.EmitStflg((int)PState.CBit);
} }
public static void EmitAddsVCheck(AilEmitterCtx context) public static void EmitAddsVCheck(ILEmitterCtx context)
{ {
//V = (Rd ^ Rn) & ~(Rn ^ Rm) < 0 //V = (Rd ^ Rn) & ~(Rn ^ Rm) < 0
context.Emit(OpCodes.Dup); context.Emit(OpCodes.Dup);
@ -63,17 +63,17 @@ namespace ChocolArm64.Instruction
context.Emit(OpCodes.Clt); context.Emit(OpCodes.Clt);
context.EmitStflg((int)ApState.VBit); context.EmitStflg((int)PState.VBit);
} }
public static void EmitSbcsCCheck(AilEmitterCtx context) public static void EmitSbcsCCheck(ILEmitterCtx context)
{ {
//C = (Rn == Rm && CIn) || Rn > Rm //C = (Rn == Rm && CIn) || Rn > Rm
EmitDataLoadOpers(context); EmitDataLoadOpers(context);
context.Emit(OpCodes.Ceq); context.Emit(OpCodes.Ceq);
context.EmitLdflg((int)ApState.CBit); context.EmitLdflg((int)PState.CBit);
context.Emit(OpCodes.And); context.Emit(OpCodes.And);
@ -82,10 +82,10 @@ namespace ChocolArm64.Instruction
context.Emit(OpCodes.Cgt_Un); context.Emit(OpCodes.Cgt_Un);
context.Emit(OpCodes.Or); context.Emit(OpCodes.Or);
context.EmitStflg((int)ApState.CBit); context.EmitStflg((int)PState.CBit);
} }
public static void EmitSubsCCheck(AilEmitterCtx context) public static void EmitSubsCCheck(ILEmitterCtx context)
{ {
//C = Rn == Rm || Rn > Rm = !(Rn < Rm) //C = Rn == Rm || Rn > Rm = !(Rn < Rm)
EmitDataLoadOpers(context); EmitDataLoadOpers(context);
@ -96,10 +96,10 @@ namespace ChocolArm64.Instruction
context.Emit(OpCodes.Xor); context.Emit(OpCodes.Xor);
context.EmitStflg((int)ApState.CBit); context.EmitStflg((int)PState.CBit);
} }
public static void EmitSubsVCheck(AilEmitterCtx context) public static void EmitSubsVCheck(ILEmitterCtx context)
{ {
//V = (Rd ^ Rn) & (Rn ^ Rm) < 0 //V = (Rd ^ Rn) & (Rn ^ Rm) < 0
context.Emit(OpCodes.Dup); context.Emit(OpCodes.Dup);
@ -117,25 +117,25 @@ namespace ChocolArm64.Instruction
context.Emit(OpCodes.Clt); context.Emit(OpCodes.Clt);
context.EmitStflg((int)ApState.VBit); context.EmitStflg((int)PState.VBit);
} }
public static void EmitDataLoadRm(AilEmitterCtx context) public static void EmitDataLoadRm(ILEmitterCtx context)
{ {
context.EmitLdintzr(((IaOpCodeAluRs)context.CurrOp).Rm); context.EmitLdintzr(((IOpCodeAluRs)context.CurrOp).Rm);
} }
public static void EmitDataLoadOpers(AilEmitterCtx context) public static void EmitDataLoadOpers(ILEmitterCtx context)
{ {
EmitDataLoadRn(context); EmitDataLoadRn(context);
EmitDataLoadOper2(context); EmitDataLoadOper2(context);
} }
public static void EmitDataLoadRn(AilEmitterCtx context) public static void EmitDataLoadRn(ILEmitterCtx context)
{ {
IaOpCodeAlu op = (IaOpCodeAlu)context.CurrOp; IOpCodeAlu op = (IOpCodeAlu)context.CurrOp;
if (op.DataOp == ADataOp.Logical || op is IaOpCodeAluRs) if (op.DataOp == DataOp.Logical || op is IOpCodeAluRs)
{ {
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
} }
@ -145,27 +145,27 @@ namespace ChocolArm64.Instruction
} }
} }
public static void EmitDataLoadOper2(AilEmitterCtx context) public static void EmitDataLoadOper2(ILEmitterCtx context)
{ {
switch (context.CurrOp) switch (context.CurrOp)
{ {
case IaOpCodeAluImm op: case IOpCodeAluImm op:
context.EmitLdc_I(op.Imm); context.EmitLdc_I(op.Imm);
break; break;
case IaOpCodeAluRs op: case IOpCodeAluRs op:
context.EmitLdintzr(op.Rm); context.EmitLdintzr(op.Rm);
switch (op.ShiftType) switch (op.ShiftType)
{ {
case AShiftType.Lsl: context.EmitLsl(op.Shift); break; case ShiftType.Lsl: context.EmitLsl(op.Shift); break;
case AShiftType.Lsr: context.EmitLsr(op.Shift); break; case ShiftType.Lsr: context.EmitLsr(op.Shift); break;
case AShiftType.Asr: context.EmitAsr(op.Shift); break; case ShiftType.Asr: context.EmitAsr(op.Shift); break;
case AShiftType.Ror: context.EmitRor(op.Shift); break; case ShiftType.Ror: context.EmitRor(op.Shift); break;
} }
break; break;
case IaOpCodeAluRx op: case IOpCodeAluRx op:
context.EmitLdintzr(op.Rm); context.EmitLdintzr(op.Rm);
context.EmitCast(op.IntType); context.EmitCast(op.IntType);
context.EmitLsl(op.Shift); context.EmitLsl(op.Shift);
@ -173,14 +173,14 @@ namespace ChocolArm64.Instruction
} }
} }
public static void EmitDataStore(AilEmitterCtx context) => EmitDataStore(context, false); public static void EmitDataStore(ILEmitterCtx context) => EmitDataStore(context, false);
public static void EmitDataStoreS(AilEmitterCtx context) => EmitDataStore(context, true); public static void EmitDataStoreS(ILEmitterCtx context) => EmitDataStore(context, true);
public static void EmitDataStore(AilEmitterCtx context, bool setFlags) public static void EmitDataStore(ILEmitterCtx context, bool setFlags)
{ {
IaOpCodeAlu op = (IaOpCodeAlu)context.CurrOp; IOpCodeAlu op = (IOpCodeAlu)context.CurrOp;
if (setFlags || op is IaOpCodeAluRs) if (setFlags || op is IOpCodeAluRs)
{ {
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
} }
@ -190,23 +190,23 @@ namespace ChocolArm64.Instruction
} }
} }
public static void EmitSetNzcv(AilEmitterCtx context, int nzcv) public static void EmitSetNzcv(ILEmitterCtx context, int nzcv)
{ {
context.EmitLdc_I4((nzcv >> 0) & 1); context.EmitLdc_I4((nzcv >> 0) & 1);
context.EmitStflg((int)ApState.VBit); context.EmitStflg((int)PState.VBit);
context.EmitLdc_I4((nzcv >> 1) & 1); context.EmitLdc_I4((nzcv >> 1) & 1);
context.EmitStflg((int)ApState.CBit); context.EmitStflg((int)PState.CBit);
context.EmitLdc_I4((nzcv >> 2) & 1); context.EmitLdc_I4((nzcv >> 2) & 1);
context.EmitStflg((int)ApState.ZBit); context.EmitStflg((int)PState.ZBit);
context.EmitLdc_I4((nzcv >> 3) & 1); context.EmitLdc_I4((nzcv >> 3) & 1);
context.EmitStflg((int)ApState.NBit); context.EmitStflg((int)PState.NBit);
} }
} }
} }

48
ChocolArm64/Instruction/AInstEmitBfm.cs → ChocolArm64/Instruction/InstEmitBfm.cs
View file

@ -5,11 +5,11 @@ using System.Reflection.Emit;
namespace ChocolArm64.Instruction namespace ChocolArm64.Instruction
{ {
static partial class AInstEmit static partial class InstEmit
{ {
public static void Bfm(AilEmitterCtx context) public static void Bfm(ILEmitterCtx context)
{ {
AOpCodeBfm op = (AOpCodeBfm)context.CurrOp; OpCodeBfm op = (OpCodeBfm)context.CurrOp;
EmitBfmLoadRn(context); EmitBfmLoadRn(context);
@ -28,9 +28,9 @@ namespace ChocolArm64.Instruction
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
} }
public static void Sbfm(AilEmitterCtx context) public static void Sbfm(ILEmitterCtx context)
{ {
AOpCodeBfm op = (AOpCodeBfm)context.CurrOp; OpCodeBfm op = (OpCodeBfm)context.CurrOp;
int bitsCount = op.GetBitsCount(); int bitsCount = op.GetBitsCount();
@ -72,9 +72,9 @@ namespace ChocolArm64.Instruction
} }
} }
public static void Ubfm(AilEmitterCtx context) public static void Ubfm(ILEmitterCtx context)
{ {
AOpCodeBfm op = (AOpCodeBfm)context.CurrOp; OpCodeBfm op = (OpCodeBfm)context.CurrOp;
if (op.Pos + 1 == op.GetBitsCount()) if (op.Pos + 1 == op.GetBitsCount())
{ {
@ -104,12 +104,12 @@ namespace ChocolArm64.Instruction
} }
} }
private static void EmitSbfiz(AilEmitterCtx context) => EmitBfiz(context, true); private static void EmitSbfiz(ILEmitterCtx context) => EmitBfiz(context, true);
private static void EmitUbfiz(AilEmitterCtx context) => EmitBfiz(context, false); private static void EmitUbfiz(ILEmitterCtx context) => EmitBfiz(context, false);
private static void EmitBfiz(AilEmitterCtx context, bool signed) private static void EmitBfiz(ILEmitterCtx context, bool signed)
{ {
AOpCodeBfm op = (AOpCodeBfm)context.CurrOp; OpCodeBfm op = (OpCodeBfm)context.CurrOp;
int width = op.Pos + 1; int width = op.Pos + 1;
@ -129,25 +129,25 @@ namespace ChocolArm64.Instruction
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
} }
private static void EmitSbfmCast(AilEmitterCtx context, OpCode ilOp) private static void EmitSbfmCast(ILEmitterCtx context, OpCode ilOp)
{ {
EmitBfmCast(context, ilOp, true); EmitBfmCast(context, ilOp, true);
} }
private static void EmitUbfmCast(AilEmitterCtx context, OpCode ilOp) private static void EmitUbfmCast(ILEmitterCtx context, OpCode ilOp)
{ {
EmitBfmCast(context, ilOp, false); EmitBfmCast(context, ilOp, false);
} }
private static void EmitBfmCast(AilEmitterCtx context, OpCode ilOp, bool signed) private static void EmitBfmCast(ILEmitterCtx context, OpCode ilOp, bool signed)
{ {
AOpCodeBfm op = (AOpCodeBfm)context.CurrOp; OpCodeBfm op = (OpCodeBfm)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
context.Emit(ilOp); context.Emit(ilOp);
if (op.RegisterSize != ARegisterSize.Int32) if (op.RegisterSize != RegisterSize.Int32)
{ {
context.Emit(signed context.Emit(signed
? OpCodes.Conv_I8 ? OpCodes.Conv_I8
@ -157,19 +157,19 @@ namespace ChocolArm64.Instruction
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
} }
private static void EmitSbfmShift(AilEmitterCtx context) private static void EmitSbfmShift(ILEmitterCtx context)
{ {
EmitBfmShift(context, true); EmitBfmShift(context, true);
} }
private static void EmitUbfmShift(AilEmitterCtx context) private static void EmitUbfmShift(ILEmitterCtx context)
{ {
EmitBfmShift(context, false); EmitBfmShift(context, false);
} }
private static void EmitBfmShift(AilEmitterCtx context, bool signed) private static void EmitBfmShift(ILEmitterCtx context, bool signed)
{ {
AOpCodeBfm op = (AOpCodeBfm)context.CurrOp; OpCodeBfm op = (OpCodeBfm)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
context.EmitLdc_I4(op.Shift); context.EmitLdc_I4(op.Shift);
@ -181,9 +181,9 @@ namespace ChocolArm64.Instruction
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
} }
private static void EmitBfmLsl(AilEmitterCtx context) private static void EmitBfmLsl(ILEmitterCtx context)
{ {
AOpCodeBfm op = (AOpCodeBfm)context.CurrOp; OpCodeBfm op = (OpCodeBfm)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
@ -192,9 +192,9 @@ namespace ChocolArm64.Instruction
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
} }
private static void EmitBfmLoadRn(AilEmitterCtx context) private static void EmitBfmLoadRn(ILEmitterCtx context)
{ {
AOpCodeBfm op = (AOpCodeBfm)context.CurrOp; OpCodeBfm op = (OpCodeBfm)context.CurrOp;
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);

24
ChocolArm64/Instruction/AInstEmitCcmp.cs → ChocolArm64/Instruction/InstEmitCcmp.cs
View file

@ -4,11 +4,11 @@ using ChocolArm64.Translation;
using System; using System;
using System.Reflection.Emit; using System.Reflection.Emit;
using static ChocolArm64.Instruction.AInstEmitAluHelper; using static ChocolArm64.Instruction.InstEmitAluHelper;
namespace ChocolArm64.Instruction namespace ChocolArm64.Instruction
{ {
static partial class AInstEmit static partial class InstEmit
{ {
private enum CcmpOp private enum CcmpOp
{ {
@ -16,33 +16,33 @@ namespace ChocolArm64.Instruction
Cmn Cmn
} }
public static void Ccmn(AilEmitterCtx context) => EmitCcmp(context, CcmpOp.Cmn); public static void Ccmn(ILEmitterCtx context) => EmitCcmp(context, CcmpOp.Cmn);
public static void Ccmp(AilEmitterCtx context) => EmitCcmp(context, CcmpOp.Cmp); public static void Ccmp(ILEmitterCtx context) => EmitCcmp(context, CcmpOp.Cmp);
private static void EmitCcmp(AilEmitterCtx context, CcmpOp cmpOp) private static void EmitCcmp(ILEmitterCtx context, CcmpOp cmpOp)
{ {
AOpCodeCcmp op = (AOpCodeCcmp)context.CurrOp; OpCodeCcmp op = (OpCodeCcmp)context.CurrOp;
AilLabel lblTrue = new AilLabel(); ILLabel lblTrue = new ILLabel();
AilLabel lblEnd = new AilLabel(); ILLabel lblEnd = new ILLabel();
context.EmitCondBranch(lblTrue, op.Cond); context.EmitCondBranch(lblTrue, op.Cond);
context.EmitLdc_I4((op.Nzcv >> 0) & 1); context.EmitLdc_I4((op.Nzcv >> 0) & 1);
context.EmitStflg((int)ApState.VBit); context.EmitStflg((int)PState.VBit);
context.EmitLdc_I4((op.Nzcv >> 1) & 1); context.EmitLdc_I4((op.Nzcv >> 1) & 1);
context.EmitStflg((int)ApState.CBit); context.EmitStflg((int)PState.CBit);
context.EmitLdc_I4((op.Nzcv >> 2) & 1); context.EmitLdc_I4((op.Nzcv >> 2) & 1);
context.EmitStflg((int)ApState.ZBit); context.EmitStflg((int)PState.ZBit);
context.EmitLdc_I4((op.Nzcv >> 3) & 1); context.EmitLdc_I4((op.Nzcv >> 3) & 1);
context.EmitStflg((int)ApState.NBit); context.EmitStflg((int)PState.NBit);
context.Emit(OpCodes.Br_S, lblEnd); context.Emit(OpCodes.Br_S, lblEnd);

18
ChocolArm64/Instruction/AInstEmitCsel.cs → ChocolArm64/Instruction/InstEmitCsel.cs
View file

@ -4,7 +4,7 @@ using System.Reflection.Emit;
namespace ChocolArm64.Instruction namespace ChocolArm64.Instruction
{ {
static partial class AInstEmit static partial class InstEmit
{ {
private enum CselOperation private enum CselOperation
{ {
@ -14,17 +14,17 @@ namespace ChocolArm64.Instruction
Negate Negate
} }
public static void Csel(AilEmitterCtx context) => EmitCsel(context, CselOperation.None); public static void Csel(ILEmitterCtx context) => EmitCsel(context, CselOperation.None);
public static void Csinc(AilEmitterCtx context) => EmitCsel(context, CselOperation.Increment); public static void Csinc(ILEmitterCtx context) => EmitCsel(context, CselOperation.Increment);
public static void Csinv(AilEmitterCtx context) => EmitCsel(context, CselOperation.Invert); public static void Csinv(ILEmitterCtx context) => EmitCsel(context, CselOperation.Invert);
public static void Csneg(AilEmitterCtx context) => EmitCsel(context, CselOperation.Negate); public static void Csneg(ILEmitterCtx context) => EmitCsel(context, CselOperation.Negate);
private static void EmitCsel(AilEmitterCtx context, CselOperation cselOp) private static void EmitCsel(ILEmitterCtx context, CselOperation cselOp)
{ {
AOpCodeCsel op = (AOpCodeCsel)context.CurrOp; OpCodeCsel op = (OpCodeCsel)context.CurrOp;
AilLabel lblTrue = new AilLabel(); ILLabel lblTrue = new ILLabel();
AilLabel lblEnd = new AilLabel(); ILLabel lblEnd = new ILLabel();
context.EmitCondBranch(lblTrue, op.Cond); context.EmitCondBranch(lblTrue, op.Cond);
context.EmitLdintzr(op.Rm); context.EmitLdintzr(op.Rm);

20
ChocolArm64/Instruction/AInstEmitException.cs → ChocolArm64/Instruction/InstEmitException.cs
View file

@ -5,25 +5,25 @@ using System.Reflection.Emit;
namespace ChocolArm64.Instruction namespace ChocolArm64.Instruction
{ {
static partial class AInstEmit static partial class InstEmit
{ {
public static void Brk(AilEmitterCtx context) public static void Brk(ILEmitterCtx context)
{ {
EmitExceptionCall(context, nameof(AThreadState.OnBreak)); EmitExceptionCall(context, nameof(AThreadState.OnBreak));
} }
public static void Svc(AilEmitterCtx context) public static void Svc(ILEmitterCtx context)
{ {
EmitExceptionCall(context, nameof(AThreadState.OnSvcCall)); EmitExceptionCall(context, nameof(AThreadState.OnSvcCall));
} }
private static void EmitExceptionCall(AilEmitterCtx context, string mthdName) private static void EmitExceptionCall(ILEmitterCtx context, string mthdName)
{ {
AOpCodeException op = (AOpCodeException)context.CurrOp; OpCodeException op = (OpCodeException)context.CurrOp;
context.EmitStoreState(); context.EmitStoreState();
context.EmitLdarg(ATranslatedSub.StateArgIdx); context.EmitLdarg(TranslatedSub.StateArgIdx);
context.EmitLdc_I8(op.Position); context.EmitLdc_I8(op.Position);
context.EmitLdc_I4(op.Id); context.EmitLdc_I4(op.Id);
@ -32,11 +32,11 @@ namespace ChocolArm64.Instruction
//Check if the thread should still be running, if it isn't then we return 0 //Check if the thread should still be running, if it isn't then we return 0
//to force a return to the dispatcher and then exit the thread. //to force a return to the dispatcher and then exit the thread.
context.EmitLdarg(ATranslatedSub.StateArgIdx); context.EmitLdarg(TranslatedSub.StateArgIdx);
context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Running)); context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Running));
AilLabel lblEnd = new AilLabel(); ILLabel lblEnd = new ILLabel();
context.Emit(OpCodes.Brtrue_S, lblEnd); context.Emit(OpCodes.Brtrue_S, lblEnd);
@ -58,13 +58,13 @@ namespace ChocolArm64.Instruction
} }
} }
public static void Und(AilEmitterCtx context) public static void Und(ILEmitterCtx context)
{ {
AOpCode op = context.CurrOp; AOpCode op = context.CurrOp;
context.EmitStoreState(); context.EmitStoreState();
context.EmitLdarg(ATranslatedSub.StateArgIdx); context.EmitLdarg(TranslatedSub.StateArgIdx);
context.EmitLdc_I8(op.Position); context.EmitLdc_I8(op.Position);
context.EmitLdc_I4(op.RawOpCode); context.EmitLdc_I4(op.RawOpCode);

54
ChocolArm64/Instruction/AInstEmitFlow.cs → ChocolArm64/Instruction/InstEmitFlow.cs
View file

@ -5,11 +5,11 @@ using System.Reflection.Emit;
namespace ChocolArm64.Instruction namespace ChocolArm64.Instruction
{ {
static partial class AInstEmit static partial class InstEmit
{ {
public static void B(AilEmitterCtx context) public static void B(ILEmitterCtx context)
{ {
AOpCodeBImmAl op = (AOpCodeBImmAl)context.CurrOp; OpCodeBImmAl op = (OpCodeBImmAl)context.CurrOp;
if (context.CurrBlock.Branch != null) if (context.CurrBlock.Branch != null)
{ {
@ -24,16 +24,16 @@ namespace ChocolArm64.Instruction
} }
} }
public static void B_Cond(AilEmitterCtx context) public static void B_Cond(ILEmitterCtx context)
{ {
AOpCodeBImmCond op = (AOpCodeBImmCond)context.CurrOp; OpCodeBImmCond op = (OpCodeBImmCond)context.CurrOp;
EmitBranch(context, op.Cond); EmitBranch(context, op.Cond);
} }
public static void Bl(AilEmitterCtx context) public static void Bl(ILEmitterCtx context)
{ {
AOpCodeBImmAl op = (AOpCodeBImmAl)context.CurrOp; OpCodeBImmAl op = (OpCodeBImmAl)context.CurrOp;
context.EmitLdc_I(op.Position + 4); context.EmitLdc_I(op.Position + 4);
context.EmitStint(AThreadState.LrIndex); context.EmitStint(AThreadState.LrIndex);
@ -49,7 +49,7 @@ namespace ChocolArm64.Instruction
context.EmitLdc_I8(op.Position + 4); context.EmitLdc_I8(op.Position + 4);
AilLabel lblContinue = new AilLabel(); ILLabel lblContinue = new ILLabel();
context.Emit(OpCodes.Beq_S, lblContinue); context.Emit(OpCodes.Beq_S, lblContinue);
context.Emit(OpCodes.Ret); context.Emit(OpCodes.Ret);
@ -68,9 +68,9 @@ namespace ChocolArm64.Instruction
} }
} }
public static void Blr(AilEmitterCtx context) public static void Blr(ILEmitterCtx context)
{ {
AOpCodeBReg op = (AOpCodeBReg)context.CurrOp; OpCodeBReg op = (OpCodeBReg)context.CurrOp;
context.EmitLdc_I(op.Position + 4); context.EmitLdc_I(op.Position + 4);
context.EmitStint(AThreadState.LrIndex); context.EmitStint(AThreadState.LrIndex);
@ -80,9 +80,9 @@ namespace ChocolArm64.Instruction
context.Emit(OpCodes.Ret); context.Emit(OpCodes.Ret);
} }
public static void Br(AilEmitterCtx context) public static void Br(ILEmitterCtx context)
{ {
AOpCodeBReg op = (AOpCodeBReg)context.CurrOp; OpCodeBReg op = (OpCodeBReg)context.CurrOp;
context.EmitStoreState(); context.EmitStoreState();
context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rn);
@ -90,12 +90,12 @@ namespace ChocolArm64.Instruction
context.Emit(OpCodes.Ret); context.Emit(OpCodes.Ret);
} }
public static void Cbnz(AilEmitterCtx context) => EmitCb(context, OpCodes.Bne_Un); public static void Cbnz(ILEmitterCtx context) => EmitCb(context, OpCodes.Bne_Un);
public static void Cbz(AilEmitterCtx context) => EmitCb(context, OpCodes.Beq); public static void Cbz(ILEmitterCtx context) => EmitCb(context, OpCodes.Beq);
private static void EmitCb(AilEmitterCtx context, OpCode ilOp) private static void EmitCb(ILEmitterCtx context, OpCode ilOp)
{ {
AOpCodeBImmCmp op = (AOpCodeBImmCmp)context.CurrOp; OpCodeBImmCmp op = (OpCodeBImmCmp)context.CurrOp;
context.EmitLdintzr(op.Rt); context.EmitLdintzr(op.Rt);
context.EmitLdc_I(0); context.EmitLdc_I(0);
@ -103,7 +103,7 @@ namespace ChocolArm64.Instruction
EmitBranch(context, ilOp); EmitBranch(context, ilOp);
} }
public static void Ret(AilEmitterCtx context) public static void Ret(ILEmitterCtx context)
{ {
context.EmitStoreState(); context.EmitStoreState();
context.EmitLdint(AThreadState.LrIndex); context.EmitLdint(AThreadState.LrIndex);
@ -111,12 +111,12 @@ namespace ChocolArm64.Instruction
context.Emit(OpCodes.Ret); context.Emit(OpCodes.Ret);
} }
public static void Tbnz(AilEmitterCtx context) => EmitTb(context, OpCodes.Bne_Un); public static void Tbnz(ILEmitterCtx context) => EmitTb(context, OpCodes.Bne_Un);
public static void Tbz(AilEmitterCtx context) => EmitTb(context, OpCodes.Beq); public static void Tbz(ILEmitterCtx context) => EmitTb(context, OpCodes.Beq);
private static void EmitTb(AilEmitterCtx context, OpCode ilOp) private static void EmitTb(ILEmitterCtx context, OpCode ilOp)
{ {
AOpCodeBImmTest op = (AOpCodeBImmTest)context.CurrOp; OpCodeBImmTest op = (OpCodeBImmTest)context.CurrOp;
context.EmitLdintzr(op.Rt); context.EmitLdintzr(op.Rt);
context.EmitLdc_I(1L << op.Pos); context.EmitLdc_I(1L << op.Pos);
@ -128,9 +128,9 @@ namespace ChocolArm64.Instruction
EmitBranch(context, ilOp); EmitBranch(context, ilOp);
} }
private static void EmitBranch(AilEmitterCtx context, ACond cond) private static void EmitBranch(ILEmitterCtx context, Cond cond)
{ {
AOpCodeBImm op = (AOpCodeBImm)context.CurrOp; OpCodeBImm op = (OpCodeBImm)context.CurrOp;
if (context.CurrBlock.Next != null && if (context.CurrBlock.Next != null &&
context.CurrBlock.Branch != null) context.CurrBlock.Branch != null)
@ -141,7 +141,7 @@ namespace ChocolArm64.Instruction
{ {
context.EmitStoreState(); context.EmitStoreState();
AilLabel lblTaken = new AilLabel(); ILLabel lblTaken = new ILLabel();
context.EmitCondBranch(lblTaken, cond); context.EmitCondBranch(lblTaken, cond);
@ -157,9 +157,9 @@ namespace ChocolArm64.Instruction
} }
} }
private static void EmitBranch(AilEmitterCtx context, OpCode ilOp) private static void EmitBranch(ILEmitterCtx context, OpCode ilOp)
{ {
AOpCodeBImm op = (AOpCodeBImm)context.CurrOp; OpCodeBImm op = (OpCodeBImm)context.CurrOp;
if (context.CurrBlock.Next != null && if (context.CurrBlock.Next != null &&
context.CurrBlock.Branch != null) context.CurrBlock.Branch != null)
@ -170,7 +170,7 @@ namespace ChocolArm64.Instruction
{ {
context.EmitStoreState(); context.EmitStoreState();
AilLabel lblTaken = new AilLabel(); ILLabel lblTaken = new ILLabel();
context.Emit(ilOp, lblTaken); context.Emit(ilOp, lblTaken);

115
ChocolArm64/Instruction/InstEmitHash.cs Normal file
View file

@ -0,0 +1,115 @@
using ChocolArm64.Decoder;
using ChocolArm64.State;
using ChocolArm64.Translation;
using System;
using System.Reflection.Emit;
using System.Runtime.Intrinsics.X86;
namespace ChocolArm64.Instruction
{
static partial class InstEmit
{
public static void Crc32b(ILEmitterCtx context)
{
EmitCrc32(context, nameof(SoftFallback.Crc32B));
}
public static void Crc32h(ILEmitterCtx context)
{
EmitCrc32(context, nameof(SoftFallback.Crc32H));
}
public static void Crc32w(ILEmitterCtx context)
{
EmitCrc32(context, nameof(SoftFallback.Crc32W));
}
public static void Crc32x(ILEmitterCtx context)
{
EmitCrc32(context, nameof(SoftFallback.Crc32X));
}
public static void Crc32cb(ILEmitterCtx context)
{
if (Optimizations.UseSse42)
{
EmitSse42Crc32(context, typeof(uint), typeof(byte));
}
else
{
EmitCrc32(context, nameof(SoftFallback.Crc32Cb));
}
}
public static void Crc32ch(ILEmitterCtx context)
{
if (Optimizations.UseSse42)
{
EmitSse42Crc32(context, typeof(uint), typeof(ushort));
}
else
{
EmitCrc32(context, nameof(SoftFallback.Crc32Ch));
}
}
public static void Crc32cw(ILEmitterCtx context)
{
if (Optimizations.UseSse42)
{
EmitSse42Crc32(context, typeof(uint), typeof(uint));
}
else
{
EmitCrc32(context, nameof(SoftFallback.Crc32Cw));
}
}
public static void Crc32cx(ILEmitterCtx context)
{
if (Optimizations.UseSse42)
{
EmitSse42Crc32(context, typeof(ulong), typeof(ulong));
}
else
{
EmitCrc32(context, nameof(SoftFallback.Crc32Cx));
}
}
private static void EmitSse42Crc32(ILEmitterCtx context, Type tCrc, Type tData)
{
OpCodeAluRs op = (OpCodeAluRs)context.CurrOp;
context.EmitLdintzr(op.Rn);
context.EmitLdintzr(op.Rm);
context.EmitCall(typeof(Sse42).GetMethod(nameof(Sse42.Crc32), new Type[] { tCrc, tData }));
context.EmitStintzr(op.Rd);
}
private static void EmitCrc32(ILEmitterCtx context, string name)
{
OpCodeAluRs op = (OpCodeAluRs)context.CurrOp;
context.EmitLdintzr(op.Rn);
if (op.RegisterSize != RegisterSize.Int32)
{
context.Emit(OpCodes.Conv_U4);
}
context.EmitLdintzr(op.Rm);
SoftFallback.EmitCall(context, name);
if (op.RegisterSize != RegisterSize.Int32)
{
context.Emit(OpCodes.Conv_U8);
}
context.EmitStintzr(op.Rd);
}
}
}

72
ChocolArm64/Instruction/AInstEmitMemory.cs → ChocolArm64/Instruction/InstEmitMemory.cs
View file

@ -2,36 +2,36 @@ using ChocolArm64.Decoder;
using ChocolArm64.Translation; using ChocolArm64.Translation;
using System.Reflection.Emit; using System.Reflection.Emit;
using static ChocolArm64.Instruction.AInstEmitMemoryHelper; using static ChocolArm64.Instruction.InstEmitMemoryHelper;
namespace ChocolArm64.Instruction namespace ChocolArm64.Instruction
{ {
static partial class AInstEmit static partial class InstEmit
{ {
public static void Adr(AilEmitterCtx context) public static void Adr(ILEmitterCtx context)
{ {
AOpCodeAdr op = (AOpCodeAdr)context.CurrOp; OpCodeAdr op = (OpCodeAdr)context.CurrOp;
context.EmitLdc_I(op.Position + op.Imm); context.EmitLdc_I(op.Position + op.Imm);
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
} }
public static void Adrp(AilEmitterCtx context) public static void Adrp(ILEmitterCtx context)
{ {
AOpCodeAdr op = (AOpCodeAdr)context.CurrOp; OpCodeAdr op = (OpCodeAdr)context.CurrOp;
context.EmitLdc_I((op.Position & ~0xfffL) + (op.Imm << 12)); context.EmitLdc_I((op.Position & ~0xfffL) + (op.Imm << 12));
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
} }
public static void Ldr(AilEmitterCtx context) => EmitLdr(context, false); public static void Ldr(ILEmitterCtx context) => EmitLdr(context, false);
public static void Ldrs(AilEmitterCtx context) => EmitLdr(context, true); public static void Ldrs(ILEmitterCtx context) => EmitLdr(context, true);
private static void EmitLdr(AilEmitterCtx context, bool signed) private static void EmitLdr(ILEmitterCtx context, bool signed)
{ {
AOpCodeMem op = (AOpCodeMem)context.CurrOp; OpCodeMem op = (OpCodeMem)context.CurrOp;
context.EmitLdarg(ATranslatedSub.MemoryArgIdx); context.EmitLdarg(TranslatedSub.MemoryArgIdx);
EmitLoadAddress(context); EmitLoadAddress(context);
@ -48,7 +48,7 @@ namespace ChocolArm64.Instruction
EmitReadZxCall(context, op.Size); EmitReadZxCall(context, op.Size);
} }
if (op is IaOpCodeSimd) if (op is IOpCodeSimd)
{ {
context.EmitStvec(op.Rt); context.EmitStvec(op.Rt);
} }
@ -60,16 +60,16 @@ namespace ChocolArm64.Instruction
EmitWBackIfNeeded(context); EmitWBackIfNeeded(context);
} }
public static void LdrLit(AilEmitterCtx context) public static void LdrLit(ILEmitterCtx context)
{ {
IaOpCodeLit op = (IaOpCodeLit)context.CurrOp; IOpCodeLit op = (IOpCodeLit)context.CurrOp;
if (op.Prefetch) if (op.Prefetch)
{ {
return; return;
} }
context.EmitLdarg(ATranslatedSub.MemoryArgIdx); context.EmitLdarg(TranslatedSub.MemoryArgIdx);
context.EmitLdc_I8(op.Imm); context.EmitLdc_I8(op.Imm);
if (op.Signed) if (op.Signed)
@ -81,7 +81,7 @@ namespace ChocolArm64.Instruction
EmitReadZxCall(context, op.Size); EmitReadZxCall(context, op.Size);
} }
if (op is IaOpCodeSimd) if (op is IOpCodeSimd)
{ {
context.EmitStvec(op.Rt); context.EmitStvec(op.Rt);
} }
@ -91,9 +91,9 @@ namespace ChocolArm64.Instruction
} }
} }
public static void Ldp(AilEmitterCtx context) public static void Ldp(ILEmitterCtx context)
{ {
AOpCodeMemPair op = (AOpCodeMemPair)context.CurrOp; OpCodeMemPair op = (OpCodeMemPair)context.CurrOp;
void EmitReadAndStore(int rt) void EmitReadAndStore(int rt)
{ {
@ -106,7 +106,7 @@ namespace ChocolArm64.Instruction
EmitReadZxCall(context, op.Size); EmitReadZxCall(context, op.Size);
} }
if (op is IaOpCodeSimd) if (op is IOpCodeSimd)
{ {
context.EmitStvec(rt); context.EmitStvec(rt);
} }
@ -116,13 +116,13 @@ namespace ChocolArm64.Instruction
} }
} }
context.EmitLdarg(ATranslatedSub.MemoryArgIdx); context.EmitLdarg(TranslatedSub.MemoryArgIdx);
EmitLoadAddress(context); EmitLoadAddress(context);
EmitReadAndStore(op.Rt); EmitReadAndStore(op.Rt);
context.EmitLdarg(ATranslatedSub.MemoryArgIdx); context.EmitLdarg(TranslatedSub.MemoryArgIdx);
context.EmitLdtmp(); context.EmitLdtmp();
context.EmitLdc_I8(1 << op.Size); context.EmitLdc_I8(1 << op.Size);
@ -133,15 +133,15 @@ namespace ChocolArm64.Instruction
EmitWBackIfNeeded(context); EmitWBackIfNeeded(context);
} }
public static void Str(AilEmitterCtx context) public static void Str(ILEmitterCtx context)
{ {
AOpCodeMem op = (AOpCodeMem)context.CurrOp; OpCodeMem op = (OpCodeMem)context.CurrOp;
context.EmitLdarg(ATranslatedSub.MemoryArgIdx); context.EmitLdarg(TranslatedSub.MemoryArgIdx);
EmitLoadAddress(context); EmitLoadAddress(context);
if (op is IaOpCodeSimd) if (op is IOpCodeSimd)
{ {
context.EmitLdvec(op.Rt); context.EmitLdvec(op.Rt);
} }
@ -155,15 +155,15 @@ namespace ChocolArm64.Instruction
EmitWBackIfNeeded(context); EmitWBackIfNeeded(context);
} }
public static void Stp(AilEmitterCtx context) public static void Stp(ILEmitterCtx context)
{ {
AOpCodeMemPair op = (AOpCodeMemPair)context.CurrOp; OpCodeMemPair op = (OpCodeMemPair)context.CurrOp;
context.EmitLdarg(ATranslatedSub.MemoryArgIdx); context.EmitLdarg(TranslatedSub.MemoryArgIdx);
EmitLoadAddress(context); EmitLoadAddress(context);
if (op is IaOpCodeSimd) if (op is IOpCodeSimd)
{ {
context.EmitLdvec(op.Rt); context.EmitLdvec(op.Rt);
} }
@ -174,13 +174,13 @@ namespace ChocolArm64.Instruction
EmitWriteCall(context, op.Size); EmitWriteCall(context, op.Size);
context.EmitLdarg(ATranslatedSub.MemoryArgIdx); context.EmitLdarg(TranslatedSub.MemoryArgIdx);
context.EmitLdtmp(); context.EmitLdtmp();
context.EmitLdc_I8(1 << op.Size); context.EmitLdc_I8(1 << op.Size);
context.Emit(OpCodes.Add); context.Emit(OpCodes.Add);
if (op is IaOpCodeSimd) if (op is IOpCodeSimd)
{ {
context.EmitLdvec(op.Rt2); context.EmitLdvec(op.Rt2);
} }
@ -194,11 +194,11 @@ namespace ChocolArm64.Instruction
EmitWBackIfNeeded(context); EmitWBackIfNeeded(context);
} }
private static void EmitLoadAddress(AilEmitterCtx context) private static void EmitLoadAddress(ILEmitterCtx context)
{ {
switch (context.CurrOp) switch (context.CurrOp)
{ {
case AOpCodeMemImm op: case OpCodeMemImm op:
context.EmitLdint(op.Rn); context.EmitLdint(op.Rn);
if (!op.PostIdx) if (!op.PostIdx)
@ -210,7 +210,7 @@ namespace ChocolArm64.Instruction
} }
break; break;
case AOpCodeMemReg op: case OpCodeMemReg op:
context.EmitLdint(op.Rn); context.EmitLdint(op.Rn);
context.EmitLdintzr(op.Rm); context.EmitLdintzr(op.Rm);
context.EmitCast(op.IntType); context.EmitCast(op.IntType);
@ -230,11 +230,11 @@ namespace ChocolArm64.Instruction
context.EmitSttmp(); context.EmitSttmp();
} }
private static void EmitWBackIfNeeded(AilEmitterCtx context) private static void EmitWBackIfNeeded(ILEmitterCtx context)
{ {
//Check whenever the current OpCode has post-indexed write back, if so write it. //Check whenever the current OpCode has post-indexed write back, if so write it.
//Note: AOpCodeMemPair inherits from AOpCodeMemImm, so this works for both. //Note: AOpCodeMemPair inherits from AOpCodeMemImm, so this works for both.
if (context.CurrOp is AOpCodeMemImm op && op.WBack) if (context.CurrOp is OpCodeMemImm op && op.WBack)
{ {
context.EmitLdtmp(); context.EmitLdtmp();

68
ChocolArm64/Instruction/AInstEmitMemoryEx.cs → ChocolArm64/Instruction/InstEmitMemoryEx.cs
View file

@ -6,11 +6,11 @@ using System;
using System.Reflection.Emit; using System.Reflection.Emit;
using System.Threading; using System.Threading;
using static ChocolArm64.Instruction.AInstEmitMemoryHelper; using static ChocolArm64.Instruction.InstEmitMemoryHelper;
namespace ChocolArm64.Instruction namespace ChocolArm64.Instruction
{ {
static partial class AInstEmit static partial class InstEmit
{ {
[Flags] [Flags]
private enum AccessType private enum AccessType
@ -21,33 +21,33 @@ namespace ChocolArm64.Instruction
OrderedEx = Ordered | Exclusive OrderedEx = Ordered | Exclusive
} }
public static void Clrex(AilEmitterCtx context) public static void Clrex(ILEmitterCtx context)
{ {
EmitMemoryCall(context, nameof(AMemory.ClearExclusive)); EmitMemoryCall(context, nameof(AMemory.ClearExclusive));
} }
public static void Dmb(AilEmitterCtx context) => EmitBarrier(context); public static void Dmb(ILEmitterCtx context) => EmitBarrier(context);
public static void Dsb(AilEmitterCtx context) => EmitBarrier(context); public static void Dsb(ILEmitterCtx context) => EmitBarrier(context);
public static void Ldar(AilEmitterCtx context) => EmitLdr(context, AccessType.Ordered); public static void Ldar(ILEmitterCtx context) => EmitLdr(context, AccessType.Ordered);
public static void Ldaxr(AilEmitterCtx context) => EmitLdr(context, AccessType.OrderedEx); public static void Ldaxr(ILEmitterCtx context) => EmitLdr(context, AccessType.OrderedEx);
public static void Ldxr(AilEmitterCtx context) => EmitLdr(context, AccessType.Exclusive); public static void Ldxr(ILEmitterCtx context) => EmitLdr(context, AccessType.Exclusive);
public static void Ldxp(AilEmitterCtx context) => EmitLdp(context, AccessType.Exclusive); public static void Ldxp(ILEmitterCtx context) => EmitLdp(context, AccessType.Exclusive);
public static void Ldaxp(AilEmitterCtx context) => EmitLdp(context, AccessType.OrderedEx); public static void Ldaxp(ILEmitterCtx context) => EmitLdp(context, AccessType.OrderedEx);
private static void EmitLdr(AilEmitterCtx context, AccessType accType) private static void EmitLdr(ILEmitterCtx context, AccessType accType)
{ {
EmitLoad(context, accType, false); EmitLoad(context, accType, false);
} }
private static void EmitLdp(AilEmitterCtx context, AccessType accType) private static void EmitLdp(ILEmitterCtx context, AccessType accType)
{ {
EmitLoad(context, accType, true); EmitLoad(context, accType, true);
} }
private static void EmitLoad(AilEmitterCtx context, AccessType accType, bool pair) private static void EmitLoad(ILEmitterCtx context, AccessType accType, bool pair)
{ {
AOpCodeMemEx op = (AOpCodeMemEx)context.CurrOp; OpCodeMemEx op = (OpCodeMemEx)context.CurrOp;
bool ordered = (accType & AccessType.Ordered) != 0; bool ordered = (accType & AccessType.Ordered) != 0;
bool exclusive = (accType & AccessType.Exclusive) != 0; bool exclusive = (accType & AccessType.Exclusive) != 0;
@ -65,7 +65,7 @@ namespace ChocolArm64.Instruction
context.EmitLdint(op.Rn); context.EmitLdint(op.Rn);
context.EmitSttmp(); context.EmitSttmp();
context.EmitLdarg(ATranslatedSub.MemoryArgIdx); context.EmitLdarg(TranslatedSub.MemoryArgIdx);
context.EmitLdtmp(); context.EmitLdtmp();
EmitReadZxCall(context, op.Size); EmitReadZxCall(context, op.Size);
@ -74,7 +74,7 @@ namespace ChocolArm64.Instruction
if (pair) if (pair)
{ {
context.EmitLdarg(ATranslatedSub.MemoryArgIdx); context.EmitLdarg(TranslatedSub.MemoryArgIdx);
context.EmitLdtmp(); context.EmitLdtmp();
context.EmitLdc_I8(1 << op.Size); context.EmitLdc_I8(1 << op.Size);
@ -86,30 +86,30 @@ namespace ChocolArm64.Instruction
} }
} }
public static void Pfrm(AilEmitterCtx context) public static void Pfrm(ILEmitterCtx context)
{ {
//Memory Prefetch, execute as no-op. //Memory Prefetch, execute as no-op.
} }
public static void Stlr(AilEmitterCtx context) => EmitStr(context, AccessType.Ordered); public static void Stlr(ILEmitterCtx context) => EmitStr(context, AccessType.Ordered);
public static void Stlxr(AilEmitterCtx context) => EmitStr(context, AccessType.OrderedEx); public static void Stlxr(ILEmitterCtx context) => EmitStr(context, AccessType.OrderedEx);
public static void Stxr(AilEmitterCtx context) => EmitStr(context, AccessType.Exclusive); public static void Stxr(ILEmitterCtx context) => EmitStr(context, AccessType.Exclusive);
public static void Stxp(AilEmitterCtx context) => EmitStp(context, AccessType.Exclusive); public static void Stxp(ILEmitterCtx context) => EmitStp(context, AccessType.Exclusive);
public static void Stlxp(AilEmitterCtx context) => EmitStp(context, AccessType.OrderedEx); public static void Stlxp(ILEmitterCtx context) => EmitStp(context, AccessType.OrderedEx);
private static void EmitStr(AilEmitterCtx context, AccessType accType) private static void EmitStr(ILEmitterCtx context, AccessType accType)
{ {
EmitStore(context, accType, false); EmitStore(context, accType, false);
} }
private static void EmitStp(AilEmitterCtx context, AccessType accType) private static void EmitStp(ILEmitterCtx context, AccessType accType)
{ {
EmitStore(context, accType, true); EmitStore(context, accType, true);
} }
private static void EmitStore(AilEmitterCtx context, AccessType accType, bool pair) private static void EmitStore(ILEmitterCtx context, AccessType accType, bool pair)
{ {
AOpCodeMemEx op = (AOpCodeMemEx)context.CurrOp; OpCodeMemEx op = (OpCodeMemEx)context.CurrOp;
bool ordered = (accType & AccessType.Ordered) != 0; bool ordered = (accType & AccessType.Ordered) != 0;
bool exclusive = (accType & AccessType.Exclusive) != 0; bool exclusive = (accType & AccessType.Exclusive) != 0;
@ -119,8 +119,8 @@ namespace ChocolArm64.Instruction
EmitBarrier(context); EmitBarrier(context);
} }
AilLabel lblEx = new AilLabel(); ILLabel lblEx = new ILLabel();
AilLabel lblEnd = new AilLabel(); ILLabel lblEnd = new ILLabel();
if (exclusive) if (exclusive)
{ {
@ -136,7 +136,7 @@ namespace ChocolArm64.Instruction
context.MarkLabel(lblEx); context.MarkLabel(lblEx);
context.EmitLdarg(ATranslatedSub.MemoryArgIdx); context.EmitLdarg(TranslatedSub.MemoryArgIdx);
context.EmitLdint(op.Rn); context.EmitLdint(op.Rn);
context.EmitLdintzr(op.Rt); context.EmitLdintzr(op.Rt);
@ -144,7 +144,7 @@ namespace ChocolArm64.Instruction
if (pair) if (pair)
{ {
context.EmitLdarg(ATranslatedSub.MemoryArgIdx); context.EmitLdarg(TranslatedSub.MemoryArgIdx);
context.EmitLdint(op.Rn); context.EmitLdint(op.Rn);
context.EmitLdc_I8(1 << op.Size); context.EmitLdc_I8(1 << op.Size);
@ -166,10 +166,10 @@ namespace ChocolArm64.Instruction
context.MarkLabel(lblEnd); context.MarkLabel(lblEnd);
} }
private static void EmitMemoryCall(AilEmitterCtx context, string name, int rn = -1) private static void EmitMemoryCall(ILEmitterCtx context, string name, int rn = -1)
{ {
context.EmitLdarg(ATranslatedSub.MemoryArgIdx); context.EmitLdarg(TranslatedSub.MemoryArgIdx);
context.EmitLdarg(ATranslatedSub.StateArgIdx); context.EmitLdarg(TranslatedSub.StateArgIdx);
context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Core)); context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Core));
@ -181,7 +181,7 @@ namespace ChocolArm64.Instruction
context.EmitCall(typeof(AMemory), name); context.EmitCall(typeof(AMemory), name);
} }
private static void EmitBarrier(AilEmitterCtx context) private static void EmitBarrier(ILEmitterCtx context)
{ {
//Note: This barrier is most likely not necessary, and probably //Note: This barrier is most likely not necessary, and probably
//doesn't make any difference since we need to do a ton of stuff //doesn't make any difference since we need to do a ton of stuff

20
ChocolArm64/Instruction/AInstEmitMemoryHelper.cs → ChocolArm64/Instruction/InstEmitMemoryHelper.cs
View file

@ -6,7 +6,7 @@ using System.Reflection.Emit;
namespace ChocolArm64.Instruction namespace ChocolArm64.Instruction
{ {
static class AInstEmitMemoryHelper static class InstEmitMemoryHelper
{ {
private enum Extension private enum Extension
{ {
@ -15,22 +15,22 @@ namespace ChocolArm64.Instruction
Sx64 Sx64
} }
public static void EmitReadZxCall(AilEmitterCtx context, int size) public static void EmitReadZxCall(ILEmitterCtx context, int size)
{ {
EmitReadCall(context, Extension.Zx, size); EmitReadCall(context, Extension.Zx, size);
} }
public static void EmitReadSx32Call(AilEmitterCtx context, int size) public static void EmitReadSx32Call(ILEmitterCtx context, int size)
{ {
EmitReadCall(context, Extension.Sx32, size); EmitReadCall(context, Extension.Sx32, size);
} }
public static void EmitReadSx64Call(AilEmitterCtx context, int size) public static void EmitReadSx64Call(ILEmitterCtx context, int size)
{ {
EmitReadCall(context, Extension.Sx64, size); EmitReadCall(context, Extension.Sx64, size);
} }
private static void EmitReadCall(AilEmitterCtx context, Extension ext, int size) private static void EmitReadCall(ILEmitterCtx context, Extension ext, int size)
{ {
bool isSimd = GetIsSimd(context); bool isSimd = GetIsSimd(context);
@ -87,7 +87,7 @@ namespace ChocolArm64.Instruction
} }
} }
public static void EmitWriteCall(AilEmitterCtx context, int size) public static void EmitWriteCall(ILEmitterCtx context, int size)
{ {
bool isSimd = GetIsSimd(context); bool isSimd = GetIsSimd(context);
@ -128,11 +128,11 @@ namespace ChocolArm64.Instruction
context.EmitCall(typeof(AMemory), name); context.EmitCall(typeof(AMemory), name);
} }
private static bool GetIsSimd(AilEmitterCtx context) private static bool GetIsSimd(ILEmitterCtx context)
{ {
return context.CurrOp is IaOpCodeSimd && return context.CurrOp is IOpCodeSimd &&
!(context.CurrOp is AOpCodeSimdMemMs || !(context.CurrOp is OpCodeSimdMemMs ||
context.CurrOp is AOpCodeSimdMemSs); context.CurrOp is OpCodeSimdMemSs);
} }
} }
} }

14
ChocolArm64/Instruction/AInstEmitMove.cs → ChocolArm64/Instruction/InstEmitMove.cs
View file

@ -4,11 +4,11 @@ using System.Reflection.Emit;
namespace ChocolArm64.Instruction namespace ChocolArm64.Instruction
{ {
static partial class AInstEmit static partial class InstEmit
{ {
public static void Movk(AilEmitterCtx context) public static void Movk(ILEmitterCtx context)
{ {
AOpCodeMov op = (AOpCodeMov)context.CurrOp; OpCodeMov op = (OpCodeMov)context.CurrOp;
context.EmitLdintzr(op.Rd); context.EmitLdintzr(op.Rd);
context.EmitLdc_I(~(0xffffL << op.Pos)); context.EmitLdc_I(~(0xffffL << op.Pos));
@ -22,17 +22,17 @@ namespace ChocolArm64.Instruction
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
} }
public static void Movn(AilEmitterCtx context) public static void Movn(ILEmitterCtx context)
{ {
AOpCodeMov op = (AOpCodeMov)context.CurrOp; OpCodeMov op = (OpCodeMov)context.CurrOp;
context.EmitLdc_I(~op.Imm); context.EmitLdc_I(~op.Imm);
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);
} }
public static void Movz(AilEmitterCtx context) public static void Movz(ILEmitterCtx context)
{ {
AOpCodeMov op = (AOpCodeMov)context.CurrOp; OpCodeMov op = (OpCodeMov)context.CurrOp;
context.EmitLdc_I(op.Imm); context.EmitLdc_I(op.Imm);
context.EmitStintzr(op.Rd); context.EmitStintzr(op.Rd);

80
ChocolArm64/Instruction/InstEmitMul.cs Normal file
View file

@ -0,0 +1,80 @@
using ChocolArm64.Decoder;
using ChocolArm64.Translation;
using System.Reflection.Emit;
namespace ChocolArm64.Instruction
{
static partial class InstEmit
{
public static void Madd(ILEmitterCtx context) => EmitMul(context, OpCodes.Add);
public static void Msub(ILEmitterCtx context) => EmitMul(context, OpCodes.Sub);
private static void EmitMul(ILEmitterCtx context, OpCode ilOp)
{
OpCodeMul op = (OpCodeMul)context.CurrOp;
context.EmitLdintzr(op.Ra);
context.EmitLdintzr(op.Rn);
context.EmitLdintzr(op.Rm);
context.Emit(OpCodes.Mul);
context.Emit(ilOp);
context.EmitStintzr(op.Rd);
}
public static void Smaddl(ILEmitterCtx context) => EmitMull(context, OpCodes.Add, true);
public static void Smsubl(ILEmitterCtx context) => EmitMull(context, OpCodes.Sub, true);
public static void Umaddl(ILEmitterCtx context) => EmitMull(context, OpCodes.Add, false);
public static void Umsubl(ILEmitterCtx context) => EmitMull(context, OpCodes.Sub, false);
private static void EmitMull(ILEmitterCtx context, OpCode addSubOp, bool signed)
{
OpCodeMul op = (OpCodeMul)context.CurrOp;
OpCode castOp = signed
? OpCodes.Conv_I8
: OpCodes.Conv_U8;
context.EmitLdintzr(op.Ra);
context.EmitLdintzr(op.Rn);
context.Emit(OpCodes.Conv_I4);
context.Emit(castOp);
context.EmitLdintzr(op.Rm);
context.Emit(OpCodes.Conv_I4);
context.Emit(castOp);
context.Emit(OpCodes.Mul);
context.Emit(addSubOp);
context.EmitStintzr(op.Rd);
}
public static void Smulh(ILEmitterCtx context)
{
OpCodeMul op = (OpCodeMul)context.CurrOp;
context.EmitLdintzr(op.Rn);
context.EmitLdintzr(op.Rm);
SoftFallback.EmitCall(context, nameof(SoftFallback.SMulHi128));
context.EmitStintzr(op.Rd);
}
public static void Umulh(ILEmitterCtx context)
{
OpCodeMul op = (OpCodeMul)context.CurrOp;
context.EmitLdintzr(op.Rn);
context.EmitLdintzr(op.Rm);
SoftFallback.EmitCall(context, nameof(SoftFallback.UMulHi128));
context.EmitStintzr(op.Rd);
}
}
}

584
ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs → ChocolArm64/Instruction/InstEmitSimdArithmetic.cs
View file

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