Update CpuTestSimd.cs
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@ -85,6 +85,75 @@ namespace Ryujinx.Tests.Cpu
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0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _1S_F_()
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{
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return new ulong[]
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{
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0x00000000FFFFFFFFul, // -QNaN (all ones payload)
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0x00000000FFBFFFFFul, // -SNaN (all ones payload)
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0x00000000FF800000ul, // -INF
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0x00000000FF7FFFFFul, // -Max Normal, float.MinValue
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0x0000000080800000ul, // -Min Normal
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0x00000000807FFFFFul, // -Max SubNormal
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0x0000000080000001ul, // -Min SubNormal
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0x0000000080000000ul, // -0
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0x0000000000000000ul, // +0
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0x0000000000000001ul, // +Min SubNormal
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0x00000000007FFFFFul, // +Max SubNormal
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0x0000000000800000ul, // +Min Normal
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0x000000007F7FFFFFul, // +Max Normal, float.MaxValue
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0x000000007F800000ul, // +INF
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0x000000007FBFFFFFul, // +SNaN (all ones payload)
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0x000000007FFFFFFFul // +QNaN (all ones payload)
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};
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}
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private static ulong[] _2S_F_()
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{
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return new ulong[]
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{
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0xFFFFFFFFFFFFFFFFul, // -QNaN (all ones payload)
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0xFFBFFFFFFFBFFFFFul, // -SNaN (all ones payload)
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0xFF800000FF800000ul, // -INF
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0xFF7FFFFFFF7FFFFFul, // -Max Normal, float.MinValue
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0x8080000080800000ul, // -Min Normal
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0x807FFFFF807FFFFFul, // -Max SubNormal
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0x8000000180000001ul, // -Min SubNormal
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0x8000000080000000ul, // -0
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0x0000000000000000ul, // +0
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0x0000000100000001ul, // +Min SubNormal
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0x007FFFFF007FFFFFul, // +Max SubNormal
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0x0080000000800000ul, // +Min Normal
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0x7F7FFFFF7F7FFFFFul, // +Max Normal, float.MaxValue
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0x7F8000007F800000ul, // +INF
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0x7FBFFFFF7FBFFFFFul, // +SNaN (all ones payload)
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0x7FFFFFFF7FFFFFFFul // +QNaN (all ones payload)
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};
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}
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private static ulong[] _1D_F_()
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{
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return new ulong[]
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{
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0xFFFFFFFFFFFFFFFFul, // -QNaN (all ones payload)
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0xFFF7FFFFFFFFFFFFul, // -SNaN (all ones payload)
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0xFFF0000000000000ul, // -INF
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0xFFEFFFFFFFFFFFFFul, // -Max Normal, double.MinValue
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0x8010000000000000ul, // -Min Normal
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0x800FFFFFFFFFFFFFul, // -Max SubNormal
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0x8000000000000001ul, // -Min SubNormal
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0x8000000000000000ul, // -0
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0x0000000000000000ul, // +0
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0x0000000000000001ul, // +Min SubNormal
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0x000FFFFFFFFFFFFFul, // +Max SubNormal
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0x0010000000000000ul, // +Min Normal
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0x7FEFFFFFFFFFFFFFul, // +Max Normal, double.MaxValue
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0x7FF0000000000000ul, // +INF
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0x7FF7FFFFFFFFFFFFul, // +SNaN (all ones payload)
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0x7FFFFFFFFFFFFFFFul // +QNaN (all ones payload)
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};
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}
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#endregion
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private const int RndCnt = 1;
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@ -800,6 +869,242 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[Test, Pairwise, Description("FCVTNS <V><d>, <V><n>")]
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public void Fcvtns_S_S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1S_F_")] [Random(RndCnt * 2)] ulong Z,
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[ValueSource("_1S_F_")] [Random(RndCnt * 2)] ulong A)
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{
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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//const int IDCFlagBit = 7; // Input Denormal cumulative floating-point exception bit.
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//const int IXCFlagBit = 4; // Inexact cumulative floating-point exception bit.
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//const int IOCFlagBit = 0; // Invalid Operation cumulative floating-point exception bit.
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uint Opcode = 0x5E21A800; // FCVTNS S0, S0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Bits Op = new Bits(Opcode);
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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//Shared.FPCR = new Bits((uint)Fpcr);
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SimdFp.Fcvtns_S(Op[22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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/*Assert.Multiple(() =>
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{
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Assert.That(((ThreadState.Fpsr >> IDCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IDCFlagBit]));
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Assert.That(((ThreadState.Fpsr >> IXCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IXCFlagBit]));
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Assert.That(((ThreadState.Fpsr >> IOCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IOCFlagBit]));
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});*/
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}
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[Test, Pairwise, Description("FCVTNS <V><d>, <V><n>")]
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public void Fcvtns_S_D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_F_")] [Random(RndCnt * 2)] ulong Z,
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[ValueSource("_1D_F_")] [Random(RndCnt * 2)] ulong A)
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{
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uint Opcode = 0x5E61A800; // FCVTNS D0, D0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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SimdFp.Fcvtns_S(Op[22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Pairwise, Description("FCVTNS <Vd>.<T>, <Vn>.<T>")]
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public void Fcvtns_V_2S_4S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_2S_F_")] [Random(RndCnt * 2)] ulong Z,
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[ValueSource("_2S_F_")] [Random(RndCnt * 2)] ulong A,
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[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
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{
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uint Opcode = 0x0E21A800; // FCVTNS V0.2S, V0.2S
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((Q & 1) << 30);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A * Q));
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SimdFp.Fcvtns_V(Op[30], Op[22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Pairwise, Description("FCVTNS <Vd>.<T>, <Vn>.<T>")]
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public void Fcvtns_V_2D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_F_")] [Random(RndCnt * 2)] ulong Z,
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[ValueSource("_1D_F_")] [Random(RndCnt * 2)] ulong A)
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{
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uint Opcode = 0x4E61A800; // FCVTNS V0.2D, V0.2D
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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SimdFp.Fcvtns_V(Op[30], Op[22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Pairwise, Description("FCVTNU <V><d>, <V><n>")]
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public void Fcvtnu_S_S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1S_F_")] [Random(RndCnt * 2)] ulong Z,
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[ValueSource("_1S_F_")] [Random(RndCnt * 2)] ulong A)
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{
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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//const int IDCFlagBit = 7; // Input Denormal cumulative floating-point exception bit.
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//const int IXCFlagBit = 4; // Inexact cumulative floating-point exception bit.
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//const int IOCFlagBit = 0; // Invalid Operation cumulative floating-point exception bit.
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uint Opcode = 0x7E21A800; // FCVTNU S0, S0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Bits Op = new Bits(Opcode);
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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//Shared.FPCR = new Bits((uint)Fpcr);
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SimdFp.Fcvtnu_S(Op[22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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/*Assert.Multiple(() =>
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{
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Assert.That(((ThreadState.Fpsr >> IDCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IDCFlagBit]));
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Assert.That(((ThreadState.Fpsr >> IXCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IXCFlagBit]));
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Assert.That(((ThreadState.Fpsr >> IOCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IOCFlagBit]));
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});*/
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}
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[Test, Pairwise, Description("FCVTNU <V><d>, <V><n>")]
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public void Fcvtnu_S_D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_F_")] [Random(RndCnt * 2)] ulong Z,
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[ValueSource("_1D_F_")] [Random(RndCnt * 2)] ulong A)
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{
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uint Opcode = 0x7E61A800; // FCVTNU D0, D0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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SimdFp.Fcvtnu_S(Op[22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Pairwise, Description("FCVTNU <Vd>.<T>, <Vn>.<T>")]
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public void Fcvtnu_V_2S_4S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_2S_F_")] [Random(RndCnt * 2)] ulong Z,
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[ValueSource("_2S_F_")] [Random(RndCnt * 2)] ulong A,
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[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
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{
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uint Opcode = 0x2E21A800; // FCVTNU V0.2S, V0.2S
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((Q & 1) << 30);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A * Q));
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SimdFp.Fcvtnu_V(Op[30], Op[22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Pairwise, Description("FCVTNU <Vd>.<T>, <Vn>.<T>")]
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public void Fcvtnu_V_2D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_F_")] [Random(RndCnt * 2)] ulong Z,
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[ValueSource("_1D_F_")] [Random(RndCnt * 2)] ulong A)
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{
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uint Opcode = 0x6E61A800; // FCVTNU V0.2D, V0.2D
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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SimdFp.Fcvtnu_V(Op[30], Op[22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("NEG <V><d>, <V><n>")]
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public void Neg_S_D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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