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Add (failing) interrupt-related tests
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Pokechu22
parent
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commit
94169b3c7d
4 changed files with 305 additions and 0 deletions
77
Source/DSPSpy/tests/interrupt_nested.ds
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77
Source/DSPSpy/tests/interrupt_nested.ds
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; This test needs to manually specify IRQs
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jmp irq0
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jmp irq1
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jmp irq2
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jmp irq3
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jmp irq4
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jmp accov_irq
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jmp irq6
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jmp irq7
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incdir "tests"
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include "dsp_base_noirq.inc"
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test_main:
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; Use the accelerator to generate an IRQ by setting the start and end address to 0
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; This will result in an interrupt on every read
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SI @0xffda, #0 ; pred_scale
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SI @0xffdb, #0 ; yn1
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SI @0xffdc, #0 ; yn2
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SI @0xffd1, #0 ; SampleFormat
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SI @ACSAH, #0
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SI @ACCAH, #0
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SI @ACSAL, #0
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SI @ACCAL, #0
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SI @ACEAH, #0
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SI @ACEAL, #0
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CLR $ACC0
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CLR $ACC1
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LRIS $AX0.H, #1
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LRIS $AX1.H, #0
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CALL send_back
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LRS $AX0.L, @ARAM ; Trigger interrupt
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LRIS $AX1.H, #1
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LRIS $AX0.H, #2
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CALL send_back
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jmp end_of_test
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accov_irq:
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; NOTE: interrupts are NOT automatically disabled here
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; Restore registers, otherwise no new interrupt will be generated
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SI @0xffda, #0 ; pred_scale
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SI @0xffdb, #0 ; yn1
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SI @0xffdc, #0 ; yn2
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INCM $AC0.M
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INCM $AC1.M
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LRIS $AX0.H, #3
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CALL send_back
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CMPIS $AC0.M, #1
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IFZ
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; Trigger second interrupt, which will happen immediately
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LRS $AX0.L, @ARAM
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LRIS $AX1.H, #2
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LRIS $AX0.H, #4
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CALL send_back
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DECM $AC1.M
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RTI
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; Expected output ($AX0.H (send_back number), $AX1.H (changed on lines after an exception fires,
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; to make sure it happens immediately), $AC0.M (interrupt count), $AC1.M (interrupt depth), and $SR):
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; 1, 0, 0, 0, 2224 (first line)
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; 3, 0, 1, 1, 2220 (start of interrupt handler)
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; 3, 0, 2, 2, 2220 (nested start of interrupt handler)
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; 4, 2, 2, 2, 2221 (nested interrupt handler exits)
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; 4, 2, 2, 1, 2225 (interrupt handler exits)
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; 2, 1, 2, 0, 2224 (before end_of_test)
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74
Source/DSPSpy/tests/interrupt_suppressed.ds
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74
Source/DSPSpy/tests/interrupt_suppressed.ds
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; This test needs to manually specify IRQs
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jmp irq0
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jmp irq1
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jmp irq2
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jmp irq3
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jmp irq4
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jmp accov_irq
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jmp irq6
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jmp irq7
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incdir "tests"
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include "dsp_base_noirq.inc"
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test_main:
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; Use the accelerator to generate an IRQ by setting the start and end address to 0
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; This will result in an interrupt on every read
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SI @0xffda, #0 ; pred_scale
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SI @0xffdb, #0 ; yn1
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SI @0xffdc, #0 ; yn2
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SI @0xffd1, #0 ; SampleFormat
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SI @ACSAH, #0
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SI @ACCAH, #0
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SI @ACSAL, #0
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SI @ACCAL, #0
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SI @ACEAH, #0
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SI @ACEAL, #0
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CLR $ACC0
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CLR $ACC1
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LRIS $AC1.M, #1
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CALL send_back
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LRS $AX0.L, @ARAM ; Trigger interrupt
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LRIS $AC1.M, #2
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CALL send_back
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SBCLR #3 ; Disable interrupts
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LRIS $AC1.M, #3
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CALL send_back
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LRS $AX0.L, @ARAM ; Trigger interrupt while disabled
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LRIS $AC1.M, #4
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CALL send_back
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SBSET #3 ; Re-enable interrupts
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LRIS $AC1.M, #5
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CALL send_back
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jmp end_of_test
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accov_irq:
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; Restore registers, otherwise no new interrupt will be generated
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SI @0xffda, #0 ; pred_scale
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SI @0xffdb, #0 ; yn1
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SI @0xffdc, #0 ; yn2
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INCM $AC0.M
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LRIS $AC1.M, #6
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CALL send_back
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RTI
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; Expected output ($AC0.M (num interrupts), $AC1.M (send_back number), and $SR):
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; 0, 1, 2224 (start)
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; 1, 6, 2220 (in interrupt handler)
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; 1, 2, 2224 (out of interrupt handler)
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; 1, 3, 2024 (interrupts disabled)
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; 1, 4, 2024 (no interrupt triggered)
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; 1, 5, 2224 (interrupts enabled, still no interrupt triggered)
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73
Source/DSPSpy/tests/interrupt_suppressed_nested_rti.ds
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73
Source/DSPSpy/tests/interrupt_suppressed_nested_rti.ds
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@ -0,0 +1,73 @@
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; This test needs to manually specify IRQs
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jmp irq0
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jmp irq1
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jmp irq2
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jmp irq3
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jmp irq4
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jmp accov_irq
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jmp irq6
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jmp irq7
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incdir "tests"
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include "dsp_base_noirq.inc"
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test_main:
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; Use the accelerator to generate an IRQ by setting the start and end address to 0
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; This will result in an interrupt on every read
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SI @0xffda, #0 ; pred_scale
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SI @0xffdb, #0 ; yn1
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SI @0xffdc, #0 ; yn2
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SI @0xffd1, #0 ; SampleFormat
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SI @ACSAH, #0
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SI @ACCAH, #0
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SI @ACSAL, #0
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SI @ACCAL, #0
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SI @ACEAH, #0
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SI @ACEAL, #0
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CLR $ACC0
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CLR $ACC1
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LRIS $AX0.H, #1
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LRIS $AX1.H, #0
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CALL send_back
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LRS $AX0.L, @ARAM ; Trigger interrupt
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LRIS $AX1.H, #1
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LRIS $AX0.H, #2
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CALL send_back
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jmp end_of_test
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accov_irq:
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; Disable interrupts
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SBCLR #3
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; Restore registers, otherwise no new interrupt will be generated
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SI @0xffda, #0 ; pred_scale
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SI @0xffdb, #0 ; yn1
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SI @0xffdc, #0 ; yn2
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INCM $AC0.M
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INCM $AC1.M
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LRIS $AX0.H, #3
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CALL send_back
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; Trigger second interrupt, which will be ignored(!)
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LRS $AX0.L, @ARAM
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LRIS $AX1.H, #2
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LRIS $AX0.H, #4
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CALL send_back
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DECM $AC1.M
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RTI
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; Expected output ($AX0.H (send_back number), $AX1.H (changed on lines after an exception fires,
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; to make sure it happens immediately), $AC0.M (interrupt count), $AC1.M (interrupt depth), and $SR):
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; 1, 0, 0, 0, 2224 (first line)
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; 3, 0, 1, 1, 2020 (start of interrupt handler)
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; 4, 2, 1, 1, 2020 (end of interrupt handler)
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; 2, 1, 1, 0, 2224 (before end_of_test)
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81
Source/DSPSpy/tests/interrupt_suppressed_nested_sbset.ds
Normal file
81
Source/DSPSpy/tests/interrupt_suppressed_nested_sbset.ds
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@ -0,0 +1,81 @@
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; This test needs to manually specify IRQs
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jmp irq0
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jmp irq1
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jmp irq2
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jmp irq3
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jmp irq4
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jmp accov_irq
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jmp irq6
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jmp irq7
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incdir "tests"
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include "dsp_base_noirq.inc"
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test_main:
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; Use the accelerator to generate an IRQ by setting the start and end address to 0
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; This will result in an interrupt on every read
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SI @0xffda, #0 ; pred_scale
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SI @0xffdb, #0 ; yn1
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SI @0xffdc, #0 ; yn2
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SI @0xffd1, #0 ; SampleFormat
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SI @ACSAH, #0
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SI @ACCAH, #0
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SI @ACSAL, #0
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SI @ACCAL, #0
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SI @ACEAH, #0
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SI @ACEAL, #0
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CLR $ACC0
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CLR $ACC1
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LRIS $AX0.H, #1
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LRIS $AX1.H, #0
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CALL send_back
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LRS $AX0.L, @ARAM ; Trigger interrupt
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LRIS $AX1.H, #1
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LRIS $AX0.H, #2
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CALL send_back
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jmp end_of_test
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accov_irq:
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; Disable interrupts
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SBCLR #3
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; Restore registers, otherwise no new interrupt will be generated
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SI @0xffda, #0 ; pred_scale
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SI @0xffdb, #0 ; yn1
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SI @0xffdc, #0 ; yn2
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INCM $AC0.M
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INCM $AC1.M
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LRIS $AX0.H, #3
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CALL send_back
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; Trigger second interrupt, which will be ignored(!)
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LRS $AX0.L, @ARAM
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LRIS $AX1.H, #2
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LRIS $AX0.H, #4
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CALL send_back
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; Re-enable interrupts - we don't get the previously triggered interrupt here.
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SBSET #3
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LRIS $AX1.H, #3
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LRIS $AX0.H, #5
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CALL send_back
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DECM $AC1.M
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RTI
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; Expected output ($AX0.H (send_back number), $AX1.H (changed on lines after an exception fires,
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; to make sure it happens immediately), $AC0.M (interrupt count), $AC1.M (interrupt depth), and $SR):
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; 1, 0, 0, 0, 2224 (first line)
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; 3, 0, 1, 1, 2020 (start of interrupt handler)
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; 4, 2, 1, 1, 2020 (middle of interrupt handler)
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; 5, 3, 1, 1, 2220 (end of interrupt handler)
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; 2, 1, 1, 0, 2224 (before end_of_test)
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