mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-08-21 17:59:50 +00:00
Add (failing) interrupt-related tests
This commit is contained in:
Pokechu22
parent
949ca7756b
commit
94169b3c7d
4 changed files with 305 additions and 0 deletions
77
Source/DSPSpy/tests/interrupt_nested.ds
Normal file
77
Source/DSPSpy/tests/interrupt_nested.ds
Normal file
|
|
@ -0,0 +1,77 @@
|
||||||
|
; This test needs to manually specify IRQs
|
||||||
|
jmp irq0
|
||||||
|
jmp irq1
|
||||||
|
jmp irq2
|
||||||
|
jmp irq3
|
||||||
|
jmp irq4
|
||||||
|
jmp accov_irq
|
||||||
|
jmp irq6
|
||||||
|
jmp irq7
|
||||||
|
|
||||||
|
incdir "tests"
|
||||||
|
include "dsp_base_noirq.inc"
|
||||||
|
|
||||||
|
test_main:
|
||||||
|
; Use the accelerator to generate an IRQ by setting the start and end address to 0
|
||||||
|
; This will result in an interrupt on every read
|
||||||
|
SI @0xffda, #0 ; pred_scale
|
||||||
|
SI @0xffdb, #0 ; yn1
|
||||||
|
SI @0xffdc, #0 ; yn2
|
||||||
|
SI @0xffd1, #0 ; SampleFormat
|
||||||
|
SI @ACSAH, #0
|
||||||
|
SI @ACCAH, #0
|
||||||
|
SI @ACSAL, #0
|
||||||
|
SI @ACCAL, #0
|
||||||
|
SI @ACEAH, #0
|
||||||
|
SI @ACEAL, #0
|
||||||
|
|
||||||
|
CLR $ACC0
|
||||||
|
CLR $ACC1
|
||||||
|
LRIS $AX0.H, #1
|
||||||
|
LRIS $AX1.H, #0
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
LRS $AX0.L, @ARAM ; Trigger interrupt
|
||||||
|
LRIS $AX1.H, #1
|
||||||
|
|
||||||
|
LRIS $AX0.H, #2
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
jmp end_of_test
|
||||||
|
|
||||||
|
accov_irq:
|
||||||
|
; NOTE: interrupts are NOT automatically disabled here
|
||||||
|
|
||||||
|
; Restore registers, otherwise no new interrupt will be generated
|
||||||
|
SI @0xffda, #0 ; pred_scale
|
||||||
|
SI @0xffdb, #0 ; yn1
|
||||||
|
SI @0xffdc, #0 ; yn2
|
||||||
|
|
||||||
|
INCM $AC0.M
|
||||||
|
INCM $AC1.M
|
||||||
|
|
||||||
|
LRIS $AX0.H, #3
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
CMPIS $AC0.M, #1
|
||||||
|
IFZ
|
||||||
|
; Trigger second interrupt, which will happen immediately
|
||||||
|
LRS $AX0.L, @ARAM
|
||||||
|
|
||||||
|
LRIS $AX1.H, #2
|
||||||
|
|
||||||
|
LRIS $AX0.H, #4
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
DECM $AC1.M
|
||||||
|
|
||||||
|
RTI
|
||||||
|
|
||||||
|
; Expected output ($AX0.H (send_back number), $AX1.H (changed on lines after an exception fires,
|
||||||
|
; to make sure it happens immediately), $AC0.M (interrupt count), $AC1.M (interrupt depth), and $SR):
|
||||||
|
; 1, 0, 0, 0, 2224 (first line)
|
||||||
|
; 3, 0, 1, 1, 2220 (start of interrupt handler)
|
||||||
|
; 3, 0, 2, 2, 2220 (nested start of interrupt handler)
|
||||||
|
; 4, 2, 2, 2, 2221 (nested interrupt handler exits)
|
||||||
|
; 4, 2, 2, 1, 2225 (interrupt handler exits)
|
||||||
|
; 2, 1, 2, 0, 2224 (before end_of_test)
|
||||||
74
Source/DSPSpy/tests/interrupt_suppressed.ds
Normal file
74
Source/DSPSpy/tests/interrupt_suppressed.ds
Normal file
|
|
@ -0,0 +1,74 @@
|
||||||
|
; This test needs to manually specify IRQs
|
||||||
|
jmp irq0
|
||||||
|
jmp irq1
|
||||||
|
jmp irq2
|
||||||
|
jmp irq3
|
||||||
|
jmp irq4
|
||||||
|
jmp accov_irq
|
||||||
|
jmp irq6
|
||||||
|
jmp irq7
|
||||||
|
|
||||||
|
incdir "tests"
|
||||||
|
include "dsp_base_noirq.inc"
|
||||||
|
|
||||||
|
test_main:
|
||||||
|
; Use the accelerator to generate an IRQ by setting the start and end address to 0
|
||||||
|
; This will result in an interrupt on every read
|
||||||
|
SI @0xffda, #0 ; pred_scale
|
||||||
|
SI @0xffdb, #0 ; yn1
|
||||||
|
SI @0xffdc, #0 ; yn2
|
||||||
|
SI @0xffd1, #0 ; SampleFormat
|
||||||
|
SI @ACSAH, #0
|
||||||
|
SI @ACCAH, #0
|
||||||
|
SI @ACSAL, #0
|
||||||
|
SI @ACCAL, #0
|
||||||
|
SI @ACEAH, #0
|
||||||
|
SI @ACEAL, #0
|
||||||
|
|
||||||
|
CLR $ACC0
|
||||||
|
CLR $ACC1
|
||||||
|
|
||||||
|
LRIS $AC1.M, #1
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
LRS $AX0.L, @ARAM ; Trigger interrupt
|
||||||
|
|
||||||
|
LRIS $AC1.M, #2
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
SBCLR #3 ; Disable interrupts
|
||||||
|
|
||||||
|
LRIS $AC1.M, #3
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
LRS $AX0.L, @ARAM ; Trigger interrupt while disabled
|
||||||
|
|
||||||
|
LRIS $AC1.M, #4
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
SBSET #3 ; Re-enable interrupts
|
||||||
|
|
||||||
|
LRIS $AC1.M, #5
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
jmp end_of_test
|
||||||
|
|
||||||
|
accov_irq:
|
||||||
|
; Restore registers, otherwise no new interrupt will be generated
|
||||||
|
SI @0xffda, #0 ; pred_scale
|
||||||
|
SI @0xffdb, #0 ; yn1
|
||||||
|
SI @0xffdc, #0 ; yn2
|
||||||
|
|
||||||
|
INCM $AC0.M
|
||||||
|
LRIS $AC1.M, #6
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
RTI
|
||||||
|
|
||||||
|
; Expected output ($AC0.M (num interrupts), $AC1.M (send_back number), and $SR):
|
||||||
|
; 0, 1, 2224 (start)
|
||||||
|
; 1, 6, 2220 (in interrupt handler)
|
||||||
|
; 1, 2, 2224 (out of interrupt handler)
|
||||||
|
; 1, 3, 2024 (interrupts disabled)
|
||||||
|
; 1, 4, 2024 (no interrupt triggered)
|
||||||
|
; 1, 5, 2224 (interrupts enabled, still no interrupt triggered)
|
||||||
73
Source/DSPSpy/tests/interrupt_suppressed_nested_rti.ds
Normal file
73
Source/DSPSpy/tests/interrupt_suppressed_nested_rti.ds
Normal file
|
|
@ -0,0 +1,73 @@
|
||||||
|
; This test needs to manually specify IRQs
|
||||||
|
jmp irq0
|
||||||
|
jmp irq1
|
||||||
|
jmp irq2
|
||||||
|
jmp irq3
|
||||||
|
jmp irq4
|
||||||
|
jmp accov_irq
|
||||||
|
jmp irq6
|
||||||
|
jmp irq7
|
||||||
|
|
||||||
|
incdir "tests"
|
||||||
|
include "dsp_base_noirq.inc"
|
||||||
|
|
||||||
|
test_main:
|
||||||
|
; Use the accelerator to generate an IRQ by setting the start and end address to 0
|
||||||
|
; This will result in an interrupt on every read
|
||||||
|
SI @0xffda, #0 ; pred_scale
|
||||||
|
SI @0xffdb, #0 ; yn1
|
||||||
|
SI @0xffdc, #0 ; yn2
|
||||||
|
SI @0xffd1, #0 ; SampleFormat
|
||||||
|
SI @ACSAH, #0
|
||||||
|
SI @ACCAH, #0
|
||||||
|
SI @ACSAL, #0
|
||||||
|
SI @ACCAL, #0
|
||||||
|
SI @ACEAH, #0
|
||||||
|
SI @ACEAL, #0
|
||||||
|
|
||||||
|
CLR $ACC0
|
||||||
|
CLR $ACC1
|
||||||
|
LRIS $AX0.H, #1
|
||||||
|
LRIS $AX1.H, #0
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
LRS $AX0.L, @ARAM ; Trigger interrupt
|
||||||
|
LRIS $AX1.H, #1
|
||||||
|
|
||||||
|
LRIS $AX0.H, #2
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
jmp end_of_test
|
||||||
|
|
||||||
|
accov_irq:
|
||||||
|
; Disable interrupts
|
||||||
|
SBCLR #3
|
||||||
|
|
||||||
|
; Restore registers, otherwise no new interrupt will be generated
|
||||||
|
SI @0xffda, #0 ; pred_scale
|
||||||
|
SI @0xffdb, #0 ; yn1
|
||||||
|
SI @0xffdc, #0 ; yn2
|
||||||
|
|
||||||
|
INCM $AC0.M
|
||||||
|
INCM $AC1.M
|
||||||
|
|
||||||
|
LRIS $AX0.H, #3
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
; Trigger second interrupt, which will be ignored(!)
|
||||||
|
LRS $AX0.L, @ARAM
|
||||||
|
LRIS $AX1.H, #2
|
||||||
|
|
||||||
|
LRIS $AX0.H, #4
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
DECM $AC1.M
|
||||||
|
|
||||||
|
RTI
|
||||||
|
|
||||||
|
; Expected output ($AX0.H (send_back number), $AX1.H (changed on lines after an exception fires,
|
||||||
|
; to make sure it happens immediately), $AC0.M (interrupt count), $AC1.M (interrupt depth), and $SR):
|
||||||
|
; 1, 0, 0, 0, 2224 (first line)
|
||||||
|
; 3, 0, 1, 1, 2020 (start of interrupt handler)
|
||||||
|
; 4, 2, 1, 1, 2020 (end of interrupt handler)
|
||||||
|
; 2, 1, 1, 0, 2224 (before end_of_test)
|
||||||
81
Source/DSPSpy/tests/interrupt_suppressed_nested_sbset.ds
Normal file
81
Source/DSPSpy/tests/interrupt_suppressed_nested_sbset.ds
Normal file
|
|
@ -0,0 +1,81 @@
|
||||||
|
; This test needs to manually specify IRQs
|
||||||
|
jmp irq0
|
||||||
|
jmp irq1
|
||||||
|
jmp irq2
|
||||||
|
jmp irq3
|
||||||
|
jmp irq4
|
||||||
|
jmp accov_irq
|
||||||
|
jmp irq6
|
||||||
|
jmp irq7
|
||||||
|
|
||||||
|
incdir "tests"
|
||||||
|
include "dsp_base_noirq.inc"
|
||||||
|
|
||||||
|
test_main:
|
||||||
|
; Use the accelerator to generate an IRQ by setting the start and end address to 0
|
||||||
|
; This will result in an interrupt on every read
|
||||||
|
SI @0xffda, #0 ; pred_scale
|
||||||
|
SI @0xffdb, #0 ; yn1
|
||||||
|
SI @0xffdc, #0 ; yn2
|
||||||
|
SI @0xffd1, #0 ; SampleFormat
|
||||||
|
SI @ACSAH, #0
|
||||||
|
SI @ACCAH, #0
|
||||||
|
SI @ACSAL, #0
|
||||||
|
SI @ACCAL, #0
|
||||||
|
SI @ACEAH, #0
|
||||||
|
SI @ACEAL, #0
|
||||||
|
|
||||||
|
CLR $ACC0
|
||||||
|
CLR $ACC1
|
||||||
|
LRIS $AX0.H, #1
|
||||||
|
LRIS $AX1.H, #0
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
LRS $AX0.L, @ARAM ; Trigger interrupt
|
||||||
|
LRIS $AX1.H, #1
|
||||||
|
|
||||||
|
LRIS $AX0.H, #2
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
jmp end_of_test
|
||||||
|
|
||||||
|
accov_irq:
|
||||||
|
; Disable interrupts
|
||||||
|
SBCLR #3
|
||||||
|
|
||||||
|
; Restore registers, otherwise no new interrupt will be generated
|
||||||
|
SI @0xffda, #0 ; pred_scale
|
||||||
|
SI @0xffdb, #0 ; yn1
|
||||||
|
SI @0xffdc, #0 ; yn2
|
||||||
|
|
||||||
|
INCM $AC0.M
|
||||||
|
INCM $AC1.M
|
||||||
|
|
||||||
|
LRIS $AX0.H, #3
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
; Trigger second interrupt, which will be ignored(!)
|
||||||
|
LRS $AX0.L, @ARAM
|
||||||
|
LRIS $AX1.H, #2
|
||||||
|
|
||||||
|
LRIS $AX0.H, #4
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
; Re-enable interrupts - we don't get the previously triggered interrupt here.
|
||||||
|
SBSET #3
|
||||||
|
LRIS $AX1.H, #3
|
||||||
|
|
||||||
|
LRIS $AX0.H, #5
|
||||||
|
CALL send_back
|
||||||
|
|
||||||
|
DECM $AC1.M
|
||||||
|
|
||||||
|
RTI
|
||||||
|
|
||||||
|
; Expected output ($AX0.H (send_back number), $AX1.H (changed on lines after an exception fires,
|
||||||
|
; to make sure it happens immediately), $AC0.M (interrupt count), $AC1.M (interrupt depth), and $SR):
|
||||||
|
; 1, 0, 0, 0, 2224 (first line)
|
||||||
|
; 3, 0, 1, 1, 2020 (start of interrupt handler)
|
||||||
|
; 4, 2, 1, 1, 2020 (middle of interrupt handler)
|
||||||
|
; 5, 3, 1, 1, 2220 (end of interrupt handler)
|
||||||
|
; 2, 1, 1, 0, 2224 (before end_of_test)
|
||||||
Loading…
Add table
Add a link
Reference in a new issue