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Add DS_READ2ST64_B32
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parent
5c5c02cb04
commit
b1b9d22022
1 changed files with 8 additions and 6 deletions
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@ -10,13 +10,15 @@ void Translator::EmitDataShare(const GcnInst& inst) {
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case Opcode::DS_SWIZZLE_B32:
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return DS_SWIZZLE_B32(inst);
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case Opcode::DS_READ_B32:
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return DS_READ(32, false, false, inst);
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return DS_READ(32, false, false, false, inst);
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case Opcode::DS_READ2ST64_B32:
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return DS_READ(32, false, true, true, inst);
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case Opcode::DS_READ_B64:
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return DS_READ(64, false, false, inst);
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return DS_READ(64, false, false, false, inst);
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case Opcode::DS_READ2_B32:
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return DS_READ(32, false, true, inst);
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return DS_READ(32, false, true, false, inst);
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case Opcode::DS_READ2_B64:
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return DS_READ(64, false, true, inst);
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return DS_READ(64, false, true, false, inst);
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case Opcode::DS_WRITE_B32:
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return DS_WRITE(32, false, false, false, inst);
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case Opcode::DS_WRITE2ST64_B32:
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@ -65,12 +67,12 @@ void Translator::DS_SWIZZLE_B32(const GcnInst& inst) {
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SetDst(inst.dst[0], ir.QuadShuffle(src, index));
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}
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void Translator::DS_READ(int bit_size, bool is_signed, bool is_pair, const GcnInst& inst) {
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void Translator::DS_READ(int bit_size, bool is_signed, bool is_pair, bool stride64, const GcnInst& inst) {
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const IR::U32 addr{ir.GetVectorReg(IR::VectorReg(inst.src[0].code))};
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IR::VectorReg dst_reg{inst.dst[0].code};
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if (is_pair) {
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// Pair loads are either 32 or 64-bit
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const u32 adj = bit_size == 32 ? 4 : 8;
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const u32 adj = (bit_size == 32 ? 4 : 8) * (stride64 ? 64 : 1);
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0 * adj)));
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const IR::Value data0 = ir.LoadShared(bit_size, is_signed, addr0);
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if (bit_size == 32) {
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