mirrors/Ryujinx
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Update CpuTestSimd.cs

Browse source
This commit is contained in:
LDj3SNuD 2018-09-15 15:47:19 +02:00 • committed by GitHub
parent dcc00afafe
commit 145080aa26
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 12 additions and 12 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

24
Ryujinx.Tests/Cpu/CpuTestSimd.cs
View file

@ -113,11 +113,11 @@ namespace Ryujinx.Tests.Cpu
for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
{
ulong Grbg = TestContext.CurrentContext.Random.NextUInt();
ulong Val1 = GenNormal_S();
ulong Val2 = GenSubNormal_S();
ulong Rnd1 = GenNormal_S();
ulong Rnd2 = GenSubNormal_S();
yield return (Grbg << 32) | Val1;
yield return (Grbg << 32) | Val2;
yield return (Grbg << 32) | Rnd1;
yield return (Grbg << 32) | Rnd2;
}
}
@ -154,11 +154,11 @@ namespace Ryujinx.Tests.Cpu
for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
{
ulong Val1 = GenNormal_S();
ulong Val2 = GenSubNormal_S();
ulong Rnd1 = GenNormal_S();
ulong Rnd2 = GenSubNormal_S();
yield return (Val1 << 32) | Val1;
yield return (Val2 << 32) | Val2;
yield return (Rnd1 << 32) | Rnd1;
yield return (Rnd2 << 32) | Rnd2;
}
}
@ -195,11 +195,11 @@ namespace Ryujinx.Tests.Cpu
for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
{
ulong Val1 = GenNormal_D();
ulong Val2 = GenSubNormal_D();
ulong Rnd1 = GenNormal_D();
ulong Rnd2 = GenSubNormal_D();
yield return Val1;
yield return Val2;
yield return Rnd1;
yield return Rnd2;
}
}
#endregion