Update CpuTestSimdReg.cs
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1 changed files with 4 additions and 4 deletions
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@ -1151,7 +1151,7 @@ namespace Ryujinx.Tests.Cpu
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2, Fpcr: Fpcr);
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2, Fpcr: Fpcr);
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CompareAgainstUnicorn(FPSR.IOC | FPSR.DZC);
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CompareAgainstUnicorn(FpsrMask: FPSR.IOC | FPSR.DZC);
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}
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}
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[Test, Pairwise]
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[Test, Pairwise]
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@ -1168,7 +1168,7 @@ namespace Ryujinx.Tests.Cpu
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2, Fpcr: Fpcr);
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2, Fpcr: Fpcr);
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CompareAgainstUnicorn(FPSR.IOC | FPSR.DZC);
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CompareAgainstUnicorn(FpsrMask: FPSR.IOC | FPSR.DZC);
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}
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}
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[Test, Pairwise]
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[Test, Pairwise]
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@ -1192,7 +1192,7 @@ namespace Ryujinx.Tests.Cpu
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2, Fpcr: Fpcr);
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2, Fpcr: Fpcr);
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CompareAgainstUnicorn(FPSR.IOC | FPSR.DZC);
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CompareAgainstUnicorn(FpsrMask: FPSR.IOC | FPSR.DZC);
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}
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}
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[Test, Pairwise]
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[Test, Pairwise]
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@ -1214,7 +1214,7 @@ namespace Ryujinx.Tests.Cpu
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2, Fpcr: Fpcr);
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2, Fpcr: Fpcr);
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CompareAgainstUnicorn(FPSR.IOC | FPSR.DZC);
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CompareAgainstUnicorn(FpsrMask: FPSR.IOC | FPSR.DZC);
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}
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}
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[Test, Pairwise] // Fused.
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[Test, Pairwise] // Fused.
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