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Merge pull request #220 from unknownbrackets/opcodes

Browse source 
Add a few missing opcodes, fix SRAWI
This commit is contained in:
Alexandro Sánchez Bach 2014-05-09 06:23:20 +02:00
commit 8d5599d3dc
5 changed files with 85 additions and 20 deletions
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31
rpcs3/Emu/Cell/PPUDisAsm.h
View file

@ -1034,7 +1034,7 @@ private:
Write(fmt::Format("bc [%x:%x:%x:%x:%x], cr%d[%x], 0x%x, %d, %d", bo0, bo1, bo2, bo3, bo4, bi/4, bi%4, bd, aa, lk));
}
void SC(s32 sc_code)
void SC(u32 sc_code)
{
switch(sc_code)
{
@ -1320,6 +1320,10 @@ private:
{
DisAsm_R3_RC("andc", ra, rs, rb, rc);
}
void TD(u32 to, u32 ra, u32 rb)
{
DisAsm_INT1_R2("td", to, ra, rb);
}
void LVEWX(u32 vd, u32 ra, u32 rb)
{
DisAsm_V1_R2("lvewx", vd, ra, rb);
@ -1454,9 +1458,9 @@ private:
{
DisAsm_R3_OE_RC("mullw", rd, ra, rb, oe, rc);
}
void DCBTST(u32 th, u32 ra, u32 rb)
void DCBTST(u32 ra, u32 rb, u32 th)
{
DisAsm_R3("dcbtst", th, ra, rb);
DisAsm_R3("dcbtst", ra, rb, th);
}
void STBUX(u32 rs, u32 ra, u32 rb)
{
@ -1625,6 +1629,10 @@ private:
{
DisAsm_R3("ldbrx", rd, ra, rb);
}
void LSWX(u32 rd, u32 ra, u32 rb)
{
DisAsm_R3("lswx", rd, ra, rb);
}
void LWBRX(u32 rd, u32 ra, u32 rb)
{
DisAsm_R3("lwbrx", rd, ra, rb);
@ -1669,6 +1677,10 @@ private:
{
DisAsm_V1_R2("stvlx", vs, ra, rb);
}
void STSWX(u32 rs, u32 ra, u32 rb)
{
DisAsm_R3("swswx", rs, ra, rb);
}
void STWBRX(u32 rs, u32 ra, u32 rb)
{
DisAsm_R3("stwbrx", rs, ra, rb);
@ -1681,6 +1693,10 @@ private:
{
DisAsm_V1_R2("stvrx", sd, ra, rb);
}
void STFSUX(u32 frs, u32 ra, u32 rb)
{
DisAsm_F1_R2("stfsux", frs, ra, rb);
}
void STSWI(u32 rd, u32 ra, u32 nb)
{
DisAsm_R2_INT1("stswi", rd, ra, nb);
@ -1689,6 +1705,10 @@ private:
{
DisAsm_F1_R2("stfdx", frs, ra, rb);
}
void STFDUX(u32 frs, u32 ra, u32 rb)
{
DisAsm_F1_R2("stfdux", frs, ra, rb);
}
void LVLXL(u32 vd, u32 ra, u32 rb)
{
DisAsm_V1_R2("lvlxl", vd, ra, rb);
@ -1764,7 +1784,10 @@ private:
{
DisAsm_R2_RC("extsw", ra, rs, rc);
}
/*0x3d6*///ICBI
void ICBI(u32 ra, u32 rb)
{
DisAsm_R2("icbi", ra, rb);
}
void DCBZ(u32 ra, u32 rs)
{
DisAsm_R2("dcbz", ra, rs);

13
rpcs3/Emu/Cell/PPUInstrTable.h
View file

@ -470,6 +470,7 @@ namespace PPU_instr
/*0x037*/bind_instr(g1f_list, LWZUX, RD, RA, RB);
/*0x03a*/bind_instr(g1f_list, CNTLZD, RA, RS, RC);
/*0x03c*/bind_instr(g1f_list, ANDC, RA, RS, RB, RC);
/*0x03c*/bind_instr(g1f_list, TD, TO, RA, RB);
/*0x047*/bind_instr(g1f_list, LVEWX, VD, RA, RB);
/*0x049*/bind_instr(g1f_list, MULHD, RD, RA, RB, RC);
/*0x04b*/bind_instr(g1f_list, MULHW, RD, RA, RB, RC);
@ -500,7 +501,7 @@ namespace PPU_instr
/*0x0e9*/bind_instr(g1f_list, MULLD, RD, RA, RB, OE, RC);
/*0x0ea*/bind_instr(g1f_list, ADDME, RD, RA, OE, RC);
/*0x0eb*/bind_instr(g1f_list, MULLW, RD, RA, RB, OE, RC);
/*0x0f6*/bind_instr(g1f_list, DCBTST, TH, RA, RB);
/*0x0f6*/bind_instr(g1f_list, DCBTST, RA, RB, TH);
/*0x0f7*/bind_instr(g1f_list, STBUX, RS, RA, RB);
/*0x10a*/bind_instr(g1f_list, ADD, RD, RA, RB, OE, RC);
/*0x116*/bind_instr(g1f_list, DCBT, RA, RB, TH);
@ -533,6 +534,7 @@ namespace PPU_instr
/*0x1eb*/bind_instr(g1f_list, DIVW, RD, RA, RB, OE, RC);
/*0x207*/bind_instr(g1f_list, LVLX, VD, RA, RB);
/*0x214*/bind_instr(g1f_list, LDBRX, RD, RA, RB);
/*0x215*/bind_instr(g1f_list, LSWX, RD, RA, RB);
/*0x216*/bind_instr(g1f_list, LWBRX, RD, RA, RB);
/*0x217*/bind_instr(g1f_list, LFSX, FRD, RA, RB);
/*0x218*/bind_instr(g1f_list, SRW, RA, RS, RB, RC);
@ -544,18 +546,21 @@ namespace PPU_instr
/*0x257*/bind_instr(g1f_list, LFDX, FRD, RA, RB);
/*0x277*/bind_instr(g1f_list, LFDUX, FRD, RA, RB);
/*0x287*/bind_instr(g1f_list, STVLX, VS, RA, RB);
/*0x296*/bind_instr(g1f_list, STSWX, RS, RA, RB);
/*0x296*/bind_instr(g1f_list, STWBRX, RS, RA, RB);
/*0x297*/bind_instr(g1f_list, STFSX, FRS, RA, RB);
/*0x2a7*/bind_instr(g1f_list, STVRX, VS, RA, RB);
/*0x2d5*/bind_instr(g1f_list, STSWI, RD, RA, NB);
/*0x2b7*/bind_instr(g1f_list, STFSUX, FRS, RA, RB);
/*0x2d5*/bind_instr(g1f_list, STSWI, RS, RA, NB);
/*0x2d7*/bind_instr(g1f_list, STFDX, FRS, RA, RB);
/*0x2d7*/bind_instr(g1f_list, STFDUX, FRS, RA, RB);
/*0x307*/bind_instr(g1f_list, LVLXL, VD, RA, RB);
/*0x316*/bind_instr(g1f_list, LHBRX, RD, RA, RB);
/*0x318*/bind_instr(g1f_list, SRAW, RA, RS, RB, RC);
/*0x31a*/bind_instr(g1f_list, SRAD, RA, RS, RB, RC);
/*0x327*/bind_instr(g1f_list, LVRXL, VD, RA, RB);
/*0x336*/bind_instr(g1f_list, DSS, STRM, L_6);
/*0x338*/bind_instr(g1f_list, SRAWI, RA, RS, sh, RC);
/*0x338*/bind_instr(g1f_list, SRAWI, RA, RS, SH, RC);
/*0x33a*/bind_instr(g1f_list, SRADI1, RA, RS, sh, RC);
/*0x33b*/bind_instr(g1f_list, SRADI2, RA, RS, sh, RC);
/*0x356*/bind_instr(g1f_list, EIEIO);
@ -566,7 +571,7 @@ namespace PPU_instr
/*0x3ba*/bind_instr(g1f_list, EXTSB, RA, RS, RC);
/*0x3d7*/bind_instr(g1f_list, STFIWX, FRS, RA, RB);
/*0x3da*/bind_instr(g1f_list, EXTSW, RA, RS, RC);
/*0x3d6*///ICBI
/*0x3d6*/bind_instr(g1f_list, ICBI, RA, RB);
/*0x3f6*/bind_instr(g1f_list, DCBZ, RA, RB);
bind_instr(g3a_list, LD, RD, RA, DS);

43
rpcs3/Emu/Cell/PPUInterpreter.h
View file

@ -20,7 +20,7 @@
#endif
static u64 rotate_mask[64][64];
void InitRotateMask()
inline void InitRotateMask()
{
static bool inited = false;
if(inited) return;
@ -34,11 +34,11 @@ void InitRotateMask()
inited = true;
}
u8 rotl8(const u8 x, const u8 n) { return (x << n) | (x >> (8 - n)); }
u8 rotr8(const u8 x, const u8 n) { return (x >> n) | (x << (8 - n)); }
inline u8 rotl8(const u8 x, const u8 n) { return (x << n) | (x >> (8 - n)); }
inline u8 rotr8(const u8 x, const u8 n) { return (x >> n) | (x << (8 - n)); }
u16 rotl16(const u16 x, const u8 n) { return (x << n) | (x >> (16 - n)); }
u16 rotr16(const u16 x, const u8 n) { return (x >> n) | (x << (16 - n)); }
inline u16 rotl16(const u16 x, const u8 n) { return (x << n) | (x >> (16 - n)); }
inline u16 rotr16(const u16 x, const u8 n) { return (x >> n) | (x << (16 - n)); }
/*
u32 rotl32(const u32 x, const u8 n) { return (x << n) | (x >> (32 - n)); }
u32 rotr32(const u32 x, const u8 n) { return (x >> n) | (x << (32 - n)); }
@ -2088,7 +2088,7 @@ private:
}
if(lk) CPU.LR = CPU.PC + 4;
}
void SC(s32 sc_code)
void SC(u32 sc_code)
{
switch(sc_code)
{
@ -2518,6 +2518,10 @@ private:
CPU.GPR[ra] = CPU.GPR[rs] & ~CPU.GPR[rb];
if(rc) CPU.UpdateCR0<s64>(CPU.GPR[ra]);
}
void TD(u32 to, u32 ra, u32 rb)
{
UNK("td");
}
void LVEWX(u32 vd, u32 ra, u32 rb)
{
//const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~3ULL;
@ -2796,7 +2800,7 @@ private:
if(rc) CPU.UpdateCR0<s32>(CPU.GPR[rd]);
if(oe) UNK("mullwo");
}
void DCBTST(u32 th, u32 ra, u32 rb)
void DCBTST(u32 ra, u32 rb, u32 th)
{
//UNK("dcbtst", false);
_mm_mfence();
@ -3012,6 +3016,10 @@ private:
{
CPU.GPR[rd] = (u64&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]];
}
void LSWX(u32 rd, u32 ra, u32 rb)
{
UNK("lswx");
}
void LWBRX(u32 rd, u32 ra, u32 rb)
{
CPU.GPR[rd] = (u32&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]];
@ -3102,6 +3110,10 @@ private:
Memory.WriteLeft(addr, 16 - eb, CPU.VPR[vs]._u8 + eb);
}
void STSWX(u32 rs, u32 ra, u32 rb)
{
UNK("stwsx");
}
void STWBRX(u32 rs, u32 ra, u32 rb)
{
(u32&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]] = CPU.GPR[rs];
@ -3117,6 +3129,12 @@ private:
Memory.WriteRight(addr - eb, eb, CPU.VPR[vs]._u8);
}
void STFSUX(u32 frs, u32 ra, u32 rb)
{
const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
Memory.Write32(addr, CPU.FPR[frs].To32());
CPU.GPR[ra] = addr;
}
void STSWI(u32 rd, u32 ra, u32 nb)
{
u64 EA = ra ? CPU.GPR[ra] : 0;
@ -3149,6 +3167,12 @@ private:
{
Memory.Write64((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), (u64&)CPU.FPR[frs]);
}
void STFDUX(u32 frs, u32 ra, u32 rb)
{
const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
Memory.Write64(addr, (u64&)CPU.FPR[frs]);
CPU.GPR[ra] = addr;
}
void LVLXL(u32 vd, u32 ra, u32 rb)
{
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
@ -3267,7 +3291,10 @@ private:
//CPU.XER.CA = ((s64)CPU.GPR[ra] < 0); // ???
if(rc) CPU.UpdateCR0<s32>(CPU.GPR[ra]);
}
/*0x3d6*///ICBI
void ICBI(u32 ra, u32 rs)
{
// Clear jit for the specified block? Nothing to do in the interpreter.
}
void DCBZ(u32 ra, u32 rs)
{
//UNK("dcbz", false);

16
rpcs3/Emu/Cell/PPUOpcodes.h
View file

@ -280,6 +280,7 @@ namespace PPU_opcodes
LWZUX = 0x037,
CNTLZD = 0x03a,
ANDC = 0x03c,
TD = 0x044,
LVEWX = 0x047, //Load Vector Element Word Indexed
MULHD = 0x049,
MULHW = 0x04b,
@ -344,6 +345,7 @@ namespace PPU_opcodes
DIVW = 0x1eb,
LVLX = 0x207, //Load Vector Left Indexed
LDBRX = 0x214,
LSWX = 0x215,
LWBRX = 0x216,
LFSX = 0x217,
SRW = 0x218,
@ -355,11 +357,14 @@ namespace PPU_opcodes
LFDX = 0x257,
LFDUX = 0x277,
STVLX = 0x287, //Store Vector Left Indexed
STSWX = 0x295,
STWBRX = 0x296,
STFSX = 0x297,
STVRX = 0x2a7, //Store Vector Right Indexed
STFSUX = 0x2b7,
STSWI = 0x2d5,
STFDX = 0x2d7, //Store Floating-Point Double Indexed
STFDUX = 0x2f7,
LVLXL = 0x307, //Load Vector Left Indexed Last
LHBRX = 0x316,
SRAW = 0x318,
@ -623,7 +628,7 @@ public:
virtual void ADDI(u32 rd, u32 ra, s32 simm16) = 0;
virtual void ADDIS(u32 rd, u32 ra, s32 simm16) = 0;
virtual void BC(u32 bo, u32 bi, s32 bd, u32 aa, u32 lk) = 0;
virtual void SC(s32 sc_code) = 0;
virtual void SC(u32 sc_code) = 0;
virtual void B(s32 ll, u32 aa, u32 lk) = 0;
virtual void MCRF(u32 crfd, u32 crfs) = 0;
virtual void BCLR(u32 bo, u32 bi, u32 bh, u32 lk) = 0;
@ -676,6 +681,7 @@ public:
virtual void LWZUX(u32 rd, u32 ra, u32 rb) = 0;
virtual void CNTLZD(u32 ra, u32 rs, bool rc) = 0;
virtual void ANDC(u32 ra, u32 rs, u32 rb, bool rc) = 0;
virtual void TD(u32 to, u32 ra, u32 rb) = 0;
virtual void LVEWX(u32 vd, u32 ra, u32 rb) = 0;
virtual void MULHD(u32 rd, u32 ra, u32 rb, bool rc) = 0;
virtual void MULHW(u32 rd, u32 ra, u32 rb, bool rc) = 0;
@ -706,7 +712,7 @@ public:
virtual void SUBFME(u32 rd, u32 ra, u32 oe, bool rc) = 0;
virtual void ADDME(u32 rd, u32 ra, u32 oe, bool rc) = 0;
virtual void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
virtual void DCBTST(u32 th, u32 ra, u32 rb) = 0;
virtual void DCBTST(u32 ra, u32 rb, u32 th) = 0;
virtual void STBUX(u32 rs, u32 ra, u32 rb) = 0;
virtual void ADD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
virtual void DCBT(u32 ra, u32 rb, u32 th) = 0;
@ -739,6 +745,7 @@ public:
virtual void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
virtual void LVLX(u32 vd, u32 ra, u32 rb) = 0;
virtual void LDBRX(u32 rd, u32 ra, u32 rb) = 0;
virtual void LSWX(u32 rd, u32 ra, u32 rb) = 0;
virtual void LWBRX(u32 rd, u32 ra, u32 rb) = 0;
virtual void LFSX(u32 frd, u32 ra, u32 rb) = 0;
virtual void SRW(u32 ra, u32 rs, u32 rb, bool rc) = 0;
@ -750,11 +757,14 @@ public:
virtual void LFDX(u32 frd, u32 ra, u32 rb) = 0;
virtual void LFDUX(u32 frd, u32 ra, u32 rb) = 0;
virtual void STVLX(u32 vs, u32 ra, u32 rb) = 0;
virtual void STSWX(u32 rs, u32 ra, u32 rb) = 0;
virtual void STWBRX(u32 rs, u32 ra, u32 rb) = 0;
virtual void STFSX(u32 frs, u32 ra, u32 rb) = 0;
virtual void STVRX(u32 vs, u32 ra, u32 rb) = 0;
virtual void STFSUX(u32 frs, u32 ra, u32 rb) = 0;
virtual void STSWI(u32 rd, u32 ra, u32 nb) = 0;
virtual void STFDX(u32 frs, u32 ra, u32 rb) = 0;
virtual void STFDUX(u32 frs, u32 ra, u32 rb) = 0;
virtual void LVLXL(u32 vd, u32 ra, u32 rb) = 0;
virtual void LHBRX(u32 rd, u32 ra, u32 rb) = 0;
virtual void SRAW(u32 ra, u32 rs, u32 rb, bool rc) = 0;
@ -772,7 +782,7 @@ public:
virtual void EXTSB(u32 ra, u32 rs, bool rc) = 0;
virtual void STFIWX(u32 frs, u32 ra, u32 rb) = 0;
virtual void EXTSW(u32 ra, u32 rs, bool rc) = 0;
//ICBI
virtual void ICBI(u32 ra, u32 rb) = 0;
virtual void DCBZ(u32 ra, u32 rb) = 0;
virtual void LWZ(u32 rd, u32 ra, s32 d) = 0;
virtual void LWZU(u32 rd, u32 ra, s32 d) = 0;

2
wxWidgets

@ -1 +1 @@
Subproject commit 143b52a7645b140dff414f332b97f00444332bb9
Subproject commit 5a313d2c7cec6914721eac46c623fbb4211d3375